1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ 3*4882a593Smuzhiyun #define __DT_BINDINGS_POWER_RK3568_POWER_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* VD_CORE */ 6*4882a593Smuzhiyun #define RK3568_PD_CPU_0 0 7*4882a593Smuzhiyun #define RK3568_PD_CPU_1 1 8*4882a593Smuzhiyun #define RK3568_PD_CPU_2 2 9*4882a593Smuzhiyun #define RK3568_PD_CPU_3 3 10*4882a593Smuzhiyun #define RK3568_PD_CORE_ALIVE 4 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* VD_PMU */ 13*4882a593Smuzhiyun #define RK3568_PD_PMU 5 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* VD_NPU */ 16*4882a593Smuzhiyun #define RK3568_PD_NPU 6 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* VD_GPU */ 19*4882a593Smuzhiyun #define RK3568_PD_GPU 7 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* VD_LOGIC */ 22*4882a593Smuzhiyun #define RK3568_PD_VI 8 23*4882a593Smuzhiyun #define RK3568_PD_VO 9 24*4882a593Smuzhiyun #define RK3568_PD_RGA 10 25*4882a593Smuzhiyun #define RK3568_PD_VPU 11 26*4882a593Smuzhiyun #define RK3568_PD_CENTER 12 27*4882a593Smuzhiyun #define RK3568_PD_RKVDEC 13 28*4882a593Smuzhiyun #define RK3568_PD_RKVENC 14 29*4882a593Smuzhiyun #define RK3568_PD_PIPE 15 30*4882a593Smuzhiyun #define RK3568_PD_LOGIC_ALIVE 16 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #endif 33