1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __DT_BINDINGS_POWER_RK1808_POWER_H__ 3*4882a593Smuzhiyun #define __DT_BINDINGS_POWER_RK1808_POWER_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* VD_CORE */ 6*4882a593Smuzhiyun #define RK1808_PD_A35_0 0 7*4882a593Smuzhiyun #define RK1808_PD_A35_1 1 8*4882a593Smuzhiyun #define RK1808_PD_SCU 2 9*4882a593Smuzhiyun #define RK1808_VD_CORE 3 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* VD_NPU */ 12*4882a593Smuzhiyun #define RK1808_VD_NPU 4 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* VD_LOGIC */ 15*4882a593Smuzhiyun #define RK1808_PD_DDR 5 16*4882a593Smuzhiyun #define RK1808_PD_PCIE 6 17*4882a593Smuzhiyun #define RK1808_PD_VPU 7 18*4882a593Smuzhiyun #define RK1808_PD_VIO 8 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #endif 21