xref: /OK3568_Linux_fs/u-boot/include/dt-bindings/power/r8a7795-sysc.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (C) 2016 Glider bvba
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify
5*4882a593Smuzhiyun  * it under the terms of the GNU General Public License as published by
6*4882a593Smuzhiyun  * the Free Software Foundation; version 2 of the License.
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun #ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__
9*4882a593Smuzhiyun #define __DT_BINDINGS_POWER_R8A7795_SYSC_H__
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun /*
12*4882a593Smuzhiyun  * These power domain indices match the numbers of the interrupt bits
13*4882a593Smuzhiyun  * representing the power areas in the various Interrupt Registers
14*4882a593Smuzhiyun  * (e.g. SYSCISR, Interrupt Status Register)
15*4882a593Smuzhiyun  */
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #define R8A7795_PD_CA57_CPU0		 0
18*4882a593Smuzhiyun #define R8A7795_PD_CA57_CPU1		 1
19*4882a593Smuzhiyun #define R8A7795_PD_CA57_CPU2		 2
20*4882a593Smuzhiyun #define R8A7795_PD_CA57_CPU3		 3
21*4882a593Smuzhiyun #define R8A7795_PD_CA53_CPU0		 5
22*4882a593Smuzhiyun #define R8A7795_PD_CA53_CPU1		 6
23*4882a593Smuzhiyun #define R8A7795_PD_CA53_CPU2		 7
24*4882a593Smuzhiyun #define R8A7795_PD_CA53_CPU3		 8
25*4882a593Smuzhiyun #define R8A7795_PD_A3VP			 9
26*4882a593Smuzhiyun #define R8A7795_PD_CA57_SCU		12
27*4882a593Smuzhiyun #define R8A7795_PD_CR7			13
28*4882a593Smuzhiyun #define R8A7795_PD_A3VC			14
29*4882a593Smuzhiyun #define R8A7795_PD_3DG_A		17
30*4882a593Smuzhiyun #define R8A7795_PD_3DG_B		18
31*4882a593Smuzhiyun #define R8A7795_PD_3DG_C		19
32*4882a593Smuzhiyun #define R8A7795_PD_3DG_D		20
33*4882a593Smuzhiyun #define R8A7795_PD_CA53_SCU		21
34*4882a593Smuzhiyun #define R8A7795_PD_3DG_E		22
35*4882a593Smuzhiyun #define R8A7795_PD_A3IR			24
36*4882a593Smuzhiyun #define R8A7795_PD_A2VC0		25	/* ES1.x only */
37*4882a593Smuzhiyun #define R8A7795_PD_A2VC1		26
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun /* Always-on power area */
40*4882a593Smuzhiyun #define R8A7795_PD_ALWAYS_ON		32
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun #endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */
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