1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __DT_BINDINGS_POWER_PX30_POWER_H__ 8*4882a593Smuzhiyun #define __DT_BINDINGS_POWER_PX30_POWER_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* VD_CORE */ 11*4882a593Smuzhiyun #define PX30_PD_A35_0 0 12*4882a593Smuzhiyun #define PX30_PD_A35_1 1 13*4882a593Smuzhiyun #define PX30_PD_A35_2 2 14*4882a593Smuzhiyun #define PX30_PD_A35_3 3 15*4882a593Smuzhiyun #define PX30_PD_SCU 4 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* VD_LOGIC */ 18*4882a593Smuzhiyun #define PX30_PD_USB 5 19*4882a593Smuzhiyun #define PX30_PD_DDR 6 20*4882a593Smuzhiyun #define PX30_PD_SDCARD 7 21*4882a593Smuzhiyun #define PX30_PD_CRYPTO 8 22*4882a593Smuzhiyun #define PX30_PD_GMAC 9 23*4882a593Smuzhiyun #define PX30_PD_MMC_NAND 10 24*4882a593Smuzhiyun #define PX30_PD_VPU 11 25*4882a593Smuzhiyun #define PX30_PD_VO 12 26*4882a593Smuzhiyun #define PX30_PD_VI 13 27*4882a593Smuzhiyun #define PX30_PD_GPU 14 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* VD_PMU */ 30*4882a593Smuzhiyun #define PX30_PD_PMU 15 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #endif 33