1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This header provides constants for OMAP pinctrl bindings. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2009 Nokia 5*4882a593Smuzhiyun * Copyright (C) 2009-2010 Texas Instruments 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _DT_BINDINGS_PINCTRL_OMAP_H 11*4882a593Smuzhiyun #define _DT_BINDINGS_PINCTRL_OMAP_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 34xx mux mode options for each pin. See TRM for options */ 14*4882a593Smuzhiyun #define MUX_MODE0 0 15*4882a593Smuzhiyun #define MUX_MODE1 1 16*4882a593Smuzhiyun #define MUX_MODE2 2 17*4882a593Smuzhiyun #define MUX_MODE3 3 18*4882a593Smuzhiyun #define MUX_MODE4 4 19*4882a593Smuzhiyun #define MUX_MODE5 5 20*4882a593Smuzhiyun #define MUX_MODE6 6 21*4882a593Smuzhiyun #define MUX_MODE7 7 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* 24xx/34xx mux bit defines */ 24*4882a593Smuzhiyun #define PULL_ENA (1 << 3) 25*4882a593Smuzhiyun #define PULL_UP (1 << 4) 26*4882a593Smuzhiyun #define ALTELECTRICALSEL (1 << 5) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* 34xx specific mux bit defines */ 29*4882a593Smuzhiyun #define INPUT_EN (1 << 8) 30*4882a593Smuzhiyun #define OFF_EN (1 << 9) 31*4882a593Smuzhiyun #define OFFOUT_EN (1 << 10) 32*4882a593Smuzhiyun #define OFFOUT_VAL (1 << 11) 33*4882a593Smuzhiyun #define OFF_PULL_EN (1 << 12) 34*4882a593Smuzhiyun #define OFF_PULL_UP (1 << 13) 35*4882a593Smuzhiyun #define WAKEUP_EN (1 << 14) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* 44xx specific mux bit defines */ 38*4882a593Smuzhiyun #define WAKEUP_EVENT (1 << 15) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* Active pin states */ 41*4882a593Smuzhiyun #define PIN_OUTPUT 0 42*4882a593Smuzhiyun #define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP) 43*4882a593Smuzhiyun #define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA) 44*4882a593Smuzhiyun #define PIN_INPUT INPUT_EN 45*4882a593Smuzhiyun #define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) 46*4882a593Smuzhiyun #define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* Off mode states */ 49*4882a593Smuzhiyun #define PIN_OFF_NONE 0 50*4882a593Smuzhiyun #define PIN_OFF_OUTPUT_HIGH (OFF_EN | OFFOUT_EN | OFFOUT_VAL) 51*4882a593Smuzhiyun #define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN) 52*4882a593Smuzhiyun #define PIN_OFF_INPUT_PULLUP (OFF_EN | OFF_PULL_EN | OFF_PULL_UP) 53*4882a593Smuzhiyun #define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN) 54*4882a593Smuzhiyun #define PIN_OFF_WAKEUPENABLE WAKEUP_EN 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* 57*4882a593Smuzhiyun * Macros to allow using the absolute physical address instead of the 58*4882a593Smuzhiyun * padconf registers instead of the offset from padconf base. 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun #define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset)) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val) 63*4882a593Smuzhiyun #define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) 64*4882a593Smuzhiyun #define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) 65*4882a593Smuzhiyun #define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val) 66*4882a593Smuzhiyun #define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val) 67*4882a593Smuzhiyun #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) 68*4882a593Smuzhiyun #define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) 69*4882a593Smuzhiyun #define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) 70*4882a593Smuzhiyun #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* 73*4882a593Smuzhiyun * Macros to allow using the offset from the padconf physical address 74*4882a593Smuzhiyun * instead of the offset from padconf base. 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun #define OMAP_PADCONF_OFFSET(offset, base_offset) ((offset) - (base_offset)) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) 79*4882a593Smuzhiyun #define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* 82*4882a593Smuzhiyun * Define some commonly used pins configured by the boards. 83*4882a593Smuzhiyun * Note that some boards use alternative pins, so check 84*4882a593Smuzhiyun * the schematics before using these. 85*4882a593Smuzhiyun */ 86*4882a593Smuzhiyun #define OMAP3_UART1_RX 0x152 87*4882a593Smuzhiyun #define OMAP3_UART2_RX 0x14a 88*4882a593Smuzhiyun #define OMAP3_UART3_RX 0x16e 89*4882a593Smuzhiyun #define OMAP4_UART2_RX 0xdc 90*4882a593Smuzhiyun #define OMAP4_UART3_RX 0x104 91*4882a593Smuzhiyun #define OMAP4_UART4_RX 0x11c 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #endif 94*4882a593Smuzhiyun 95