1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This header provides constants for DRA pinctrl bindings. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 5*4882a593Smuzhiyun * Author: Rajendra Nayak <rnayak@ti.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 8*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 9*4882a593Smuzhiyun * published by the Free Software Foundation. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _DT_BINDINGS_PINCTRL_DRA_H 13*4882a593Smuzhiyun #define _DT_BINDINGS_PINCTRL_DRA_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* DRA7 mux mode options for each pin. See TRM for options */ 16*4882a593Smuzhiyun #define MUX_MODE0 0x0 17*4882a593Smuzhiyun #define MUX_MODE1 0x1 18*4882a593Smuzhiyun #define MUX_MODE2 0x2 19*4882a593Smuzhiyun #define MUX_MODE3 0x3 20*4882a593Smuzhiyun #define MUX_MODE4 0x4 21*4882a593Smuzhiyun #define MUX_MODE5 0x5 22*4882a593Smuzhiyun #define MUX_MODE6 0x6 23*4882a593Smuzhiyun #define MUX_MODE7 0x7 24*4882a593Smuzhiyun #define MUX_MODE8 0x8 25*4882a593Smuzhiyun #define MUX_MODE9 0x9 26*4882a593Smuzhiyun #define MUX_MODE10 0xa 27*4882a593Smuzhiyun #define MUX_MODE11 0xb 28*4882a593Smuzhiyun #define MUX_MODE12 0xc 29*4882a593Smuzhiyun #define MUX_MODE13 0xd 30*4882a593Smuzhiyun #define MUX_MODE14 0xe 31*4882a593Smuzhiyun #define MUX_MODE15 0xf 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Certain pins need virtual mode, but note: they may glitch */ 34*4882a593Smuzhiyun #define MUX_VIRTUAL_MODE0 (MODE_SELECT | (0x0 << 4)) 35*4882a593Smuzhiyun #define MUX_VIRTUAL_MODE1 (MODE_SELECT | (0x1 << 4)) 36*4882a593Smuzhiyun #define MUX_VIRTUAL_MODE2 (MODE_SELECT | (0x2 << 4)) 37*4882a593Smuzhiyun #define MUX_VIRTUAL_MODE3 (MODE_SELECT | (0x3 << 4)) 38*4882a593Smuzhiyun #define MUX_VIRTUAL_MODE4 (MODE_SELECT | (0x4 << 4)) 39*4882a593Smuzhiyun #define MUX_VIRTUAL_MODE5 (MODE_SELECT | (0x5 << 4)) 40*4882a593Smuzhiyun #define MUX_VIRTUAL_MODE6 (MODE_SELECT | (0x6 << 4)) 41*4882a593Smuzhiyun #define MUX_VIRTUAL_MODE7 (MODE_SELECT | (0x7 << 4)) 42*4882a593Smuzhiyun #define MUX_VIRTUAL_MODE8 (MODE_SELECT | (0x8 << 4)) 43*4882a593Smuzhiyun #define MUX_VIRTUAL_MODE9 (MODE_SELECT | (0x9 << 4)) 44*4882a593Smuzhiyun #define MUX_VIRTUAL_MODE10 (MODE_SELECT | (0xa << 4)) 45*4882a593Smuzhiyun #define MUX_VIRTUAL_MODE11 (MODE_SELECT | (0xb << 4)) 46*4882a593Smuzhiyun #define MUX_VIRTUAL_MODE12 (MODE_SELECT | (0xc << 4)) 47*4882a593Smuzhiyun #define MUX_VIRTUAL_MODE13 (MODE_SELECT | (0xd << 4)) 48*4882a593Smuzhiyun #define MUX_VIRTUAL_MODE14 (MODE_SELECT | (0xe << 4)) 49*4882a593Smuzhiyun #define MUX_VIRTUAL_MODE15 (MODE_SELECT | (0xf << 4)) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define MODE_SELECT (1 << 8) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define PULL_ENA (0 << 16) 54*4882a593Smuzhiyun #define PULL_DIS (1 << 16) 55*4882a593Smuzhiyun #define PULL_UP (1 << 17) 56*4882a593Smuzhiyun #define INPUT_EN (1 << 18) 57*4882a593Smuzhiyun #define SLEWCONTROL (1 << 19) 58*4882a593Smuzhiyun #define WAKEUP_EN (1 << 24) 59*4882a593Smuzhiyun #define WAKEUP_EVENT (1 << 25) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* Active pin states */ 62*4882a593Smuzhiyun #define PIN_OUTPUT (0 | PULL_DIS) 63*4882a593Smuzhiyun #define PIN_OUTPUT_PULLUP (PULL_UP) 64*4882a593Smuzhiyun #define PIN_OUTPUT_PULLDOWN (0) 65*4882a593Smuzhiyun #define PIN_INPUT (INPUT_EN | PULL_DIS) 66*4882a593Smuzhiyun #define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL) 67*4882a593Smuzhiyun #define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) 68*4882a593Smuzhiyun #define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* 71*4882a593Smuzhiyun * Macro to allow using the absolute physical address instead of the 72*4882a593Smuzhiyun * padconf registers instead of the offset from padconf base. 73*4882a593Smuzhiyun */ 74*4882a593Smuzhiyun #define DRA7XX_CORE_IOPAD(pa, val) (((pa) & 0xffff) - 0x3400) (val) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #endif 77*4882a593Smuzhiyun 78