1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * TI DP83867 PHY drivers 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _DT_BINDINGS_TI_DP83867_H 9*4882a593Smuzhiyun #define _DT_BINDINGS_TI_DP83867_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* PHY CTRL bits */ 12*4882a593Smuzhiyun #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 13*4882a593Smuzhiyun #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 14*4882a593Smuzhiyun #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 15*4882a593Smuzhiyun #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* RGMIIDCTL internal delay for rx and tx */ 18*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_250_PS 0x0 19*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_500_PS 0x1 20*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_750_PS 0x2 21*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_1_NS 0x3 22*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_1_25_NS 0x4 23*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_1_50_NS 0x5 24*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_1_75_NS 0x6 25*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_2_00_NS 0x7 26*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_2_25_NS 0x8 27*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_2_50_NS 0x9 28*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_2_75_NS 0xa 29*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_3_00_NS 0xb 30*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_3_25_NS 0xc 31*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_3_50_NS 0xd 32*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_3_75_NS 0xe 33*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_4_00_NS 0xf 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #endif 36