1*4882a593Smuzhiyun #ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H 2*4882a593Smuzhiyun #define DT_BINDINGS_MEMORY_TEGRA30_MC_H 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #define TEGRA_SWGROUP_PTC 0 5*4882a593Smuzhiyun #define TEGRA_SWGROUP_DC 1 6*4882a593Smuzhiyun #define TEGRA_SWGROUP_DCB 2 7*4882a593Smuzhiyun #define TEGRA_SWGROUP_EPP 3 8*4882a593Smuzhiyun #define TEGRA_SWGROUP_G2 4 9*4882a593Smuzhiyun #define TEGRA_SWGROUP_MPE 5 10*4882a593Smuzhiyun #define TEGRA_SWGROUP_VI 6 11*4882a593Smuzhiyun #define TEGRA_SWGROUP_AFI 7 12*4882a593Smuzhiyun #define TEGRA_SWGROUP_AVPC 8 13*4882a593Smuzhiyun #define TEGRA_SWGROUP_NV 9 14*4882a593Smuzhiyun #define TEGRA_SWGROUP_NV2 10 15*4882a593Smuzhiyun #define TEGRA_SWGROUP_HDA 11 16*4882a593Smuzhiyun #define TEGRA_SWGROUP_HC 12 17*4882a593Smuzhiyun #define TEGRA_SWGROUP_PPCS 13 18*4882a593Smuzhiyun #define TEGRA_SWGROUP_SATA 14 19*4882a593Smuzhiyun #define TEGRA_SWGROUP_VDE 15 20*4882a593Smuzhiyun #define TEGRA_SWGROUP_MPCORELP 16 21*4882a593Smuzhiyun #define TEGRA_SWGROUP_MPCORE 17 22*4882a593Smuzhiyun #define TEGRA_SWGROUP_ISP 18 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #endif 25