1*4882a593Smuzhiyun #ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H 2*4882a593Smuzhiyun #define DT_BINDINGS_MEMORY_TEGRA210_MC_H 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #define TEGRA_SWGROUP_PTC 0 5*4882a593Smuzhiyun #define TEGRA_SWGROUP_DC 1 6*4882a593Smuzhiyun #define TEGRA_SWGROUP_DCB 2 7*4882a593Smuzhiyun #define TEGRA_SWGROUP_AFI 3 8*4882a593Smuzhiyun #define TEGRA_SWGROUP_AVPC 4 9*4882a593Smuzhiyun #define TEGRA_SWGROUP_HDA 5 10*4882a593Smuzhiyun #define TEGRA_SWGROUP_HC 6 11*4882a593Smuzhiyun #define TEGRA_SWGROUP_NVENC 7 12*4882a593Smuzhiyun #define TEGRA_SWGROUP_PPCS 8 13*4882a593Smuzhiyun #define TEGRA_SWGROUP_SATA 9 14*4882a593Smuzhiyun #define TEGRA_SWGROUP_MPCORE 10 15*4882a593Smuzhiyun #define TEGRA_SWGROUP_ISP2 11 16*4882a593Smuzhiyun #define TEGRA_SWGROUP_XUSB_HOST 12 17*4882a593Smuzhiyun #define TEGRA_SWGROUP_XUSB_DEV 13 18*4882a593Smuzhiyun #define TEGRA_SWGROUP_ISP2B 14 19*4882a593Smuzhiyun #define TEGRA_SWGROUP_TSEC 15 20*4882a593Smuzhiyun #define TEGRA_SWGROUP_A9AVP 16 21*4882a593Smuzhiyun #define TEGRA_SWGROUP_GPU 17 22*4882a593Smuzhiyun #define TEGRA_SWGROUP_SDMMC1A 18 23*4882a593Smuzhiyun #define TEGRA_SWGROUP_SDMMC2A 19 24*4882a593Smuzhiyun #define TEGRA_SWGROUP_SDMMC3A 20 25*4882a593Smuzhiyun #define TEGRA_SWGROUP_SDMMC4A 21 26*4882a593Smuzhiyun #define TEGRA_SWGROUP_VIC 22 27*4882a593Smuzhiyun #define TEGRA_SWGROUP_VI 23 28*4882a593Smuzhiyun #define TEGRA_SWGROUP_NVDEC 24 29*4882a593Smuzhiyun #define TEGRA_SWGROUP_APE 25 30*4882a593Smuzhiyun #define TEGRA_SWGROUP_NVJPG 26 31*4882a593Smuzhiyun #define TEGRA_SWGROUP_SE 27 32*4882a593Smuzhiyun #define TEGRA_SWGROUP_AXIAP 28 33*4882a593Smuzhiyun #define TEGRA_SWGROUP_ETR 29 34*4882a593Smuzhiyun #define TEGRA_SWGROUP_TSECB 30 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif 37