1*4882a593Smuzhiyun #ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H 2*4882a593Smuzhiyun #define DT_BINDINGS_MEMORY_TEGRA114_MC_H 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #define TEGRA_SWGROUP_PTC 0 5*4882a593Smuzhiyun #define TEGRA_SWGROUP_DC 1 6*4882a593Smuzhiyun #define TEGRA_SWGROUP_DCB 2 7*4882a593Smuzhiyun #define TEGRA_SWGROUP_EPP 3 8*4882a593Smuzhiyun #define TEGRA_SWGROUP_G2 4 9*4882a593Smuzhiyun #define TEGRA_SWGROUP_AVPC 5 10*4882a593Smuzhiyun #define TEGRA_SWGROUP_NV 6 11*4882a593Smuzhiyun #define TEGRA_SWGROUP_HDA 7 12*4882a593Smuzhiyun #define TEGRA_SWGROUP_HC 8 13*4882a593Smuzhiyun #define TEGRA_SWGROUP_MSENC 9 14*4882a593Smuzhiyun #define TEGRA_SWGROUP_PPCS 10 15*4882a593Smuzhiyun #define TEGRA_SWGROUP_VDE 11 16*4882a593Smuzhiyun #define TEGRA_SWGROUP_MPCORELP 12 17*4882a593Smuzhiyun #define TEGRA_SWGROUP_MPCORE 13 18*4882a593Smuzhiyun #define TEGRA_SWGROUP_VI 14 19*4882a593Smuzhiyun #define TEGRA_SWGROUP_ISP 15 20*4882a593Smuzhiyun #define TEGRA_SWGROUP_XUSB_HOST 16 21*4882a593Smuzhiyun #define TEGRA_SWGROUP_XUSB_DEV 17 22*4882a593Smuzhiyun #define TEGRA_SWGROUP_EMUCIF 18 23*4882a593Smuzhiyun #define TEGRA_SWGROUP_TSEC 19 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #endif 26