1*4882a593Smuzhiyun #ifndef DT_BINDINGS_STM32_SDRAM_H 2*4882a593Smuzhiyun #define DT_BINDINGS_STM32_SDRAM_H 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #define NO_COL_8 0x0 5*4882a593Smuzhiyun #define NO_COL_9 0x1 6*4882a593Smuzhiyun #define NO_COL_10 0x2 7*4882a593Smuzhiyun #define NO_COL_11 0x3 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define NO_ROW_11 0x0 10*4882a593Smuzhiyun #define NO_ROW_12 0x1 11*4882a593Smuzhiyun #define NO_ROW_13 0x2 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define MWIDTH_8 0x0 14*4882a593Smuzhiyun #define MWIDTH_16 0x1 15*4882a593Smuzhiyun #define MWIDTH_32 0x2 16*4882a593Smuzhiyun #define BANKS_2 0x0 17*4882a593Smuzhiyun #define BANKS_4 0x1 18*4882a593Smuzhiyun #define CAS_1 0x1 19*4882a593Smuzhiyun #define CAS_2 0x2 20*4882a593Smuzhiyun #define CAS_3 0x3 21*4882a593Smuzhiyun #define SDCLK_2 0x2 22*4882a593Smuzhiyun #define RD_BURST_EN 0x1 23*4882a593Smuzhiyun #define RD_BURST_DIS 0x0 24*4882a593Smuzhiyun #define RD_PIPE_DL_0 0x0 25*4882a593Smuzhiyun #define RD_PIPE_DL_1 0x1 26*4882a593Smuzhiyun #define RD_PIPE_DL_2 0x2 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Timing = value +1 cycles */ 29*4882a593Smuzhiyun #define TMRD_2 (2 - 1) 30*4882a593Smuzhiyun #define TXSR_6 (6 - 1) 31*4882a593Smuzhiyun #define TRAS_4 (4 - 1) 32*4882a593Smuzhiyun #define TRC_6 (6 - 1) 33*4882a593Smuzhiyun #define TWR_2 (2 - 1) 34*4882a593Smuzhiyun #define TRP_2 (2 - 1) 35*4882a593Smuzhiyun #define TRCD_2 (2 - 1) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #endif 38