1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RV1126_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_DRAM_ROCKCHIP_RV1126_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define DDR2_DS_FULL (0) 10*4882a593Smuzhiyun #define DDR2_DS_REDUCE (1) 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define DDR2_ODT_DIS (0) 13*4882a593Smuzhiyun #define DDR2_ODT_50ohm (50) /* optional */ 14*4882a593Smuzhiyun #define DDR2_ODT_75ohm (75) 15*4882a593Smuzhiyun #define DDR2_ODT_150ohm (150) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define DDR3_DS_34ohm (34) 18*4882a593Smuzhiyun #define DDR3_DS_40ohm (40) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define DDR3_ODT_DIS (0) 21*4882a593Smuzhiyun #define DDR3_ODT_40ohm (40) 22*4882a593Smuzhiyun #define DDR3_ODT_60ohm (60) 23*4882a593Smuzhiyun #define DDR3_ODT_120ohm (120) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define LP2_DS_34ohm (34) 26*4882a593Smuzhiyun #define LP2_DS_40ohm (40) 27*4882a593Smuzhiyun #define LP2_DS_48ohm (48) 28*4882a593Smuzhiyun #define LP2_DS_60ohm (60) 29*4882a593Smuzhiyun #define LP2_DS_68_6ohm (68) /* optional */ 30*4882a593Smuzhiyun #define LP2_DS_80ohm (80) 31*4882a593Smuzhiyun #define LP2_DS_120ohm (120) /* optional */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define LP3_DS_34ohm (34) 34*4882a593Smuzhiyun #define LP3_DS_40ohm (40) 35*4882a593Smuzhiyun #define LP3_DS_48ohm (48) 36*4882a593Smuzhiyun #define LP3_DS_60ohm (60) 37*4882a593Smuzhiyun #define LP3_DS_80ohm (80) 38*4882a593Smuzhiyun #define LP3_DS_34D_40U (3440) 39*4882a593Smuzhiyun #define LP3_DS_40D_48U (4048) 40*4882a593Smuzhiyun #define LP3_DS_34D_48U (3448) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define LP3_ODT_DIS (0) 43*4882a593Smuzhiyun #define LP3_ODT_60ohm (60) 44*4882a593Smuzhiyun #define LP3_ODT_120ohm (120) 45*4882a593Smuzhiyun #define LP3_ODT_240ohm (240) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define LP4_PDDS_40ohm (40) 48*4882a593Smuzhiyun #define LP4_PDDS_48ohm (48) 49*4882a593Smuzhiyun #define LP4_PDDS_60ohm (60) 50*4882a593Smuzhiyun #define LP4_PDDS_80ohm (80) 51*4882a593Smuzhiyun #define LP4_PDDS_120ohm (120) 52*4882a593Smuzhiyun #define LP4_PDDS_240ohm (240) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define LP4_DQ_ODT_40ohm (40) 55*4882a593Smuzhiyun #define LP4_DQ_ODT_48ohm (48) 56*4882a593Smuzhiyun #define LP4_DQ_ODT_60ohm (60) 57*4882a593Smuzhiyun #define LP4_DQ_ODT_80ohm (80) 58*4882a593Smuzhiyun #define LP4_DQ_ODT_120ohm (120) 59*4882a593Smuzhiyun #define LP4_DQ_ODT_240ohm (240) 60*4882a593Smuzhiyun #define LP4_DQ_ODT_DIS (0) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define LP4_CA_ODT_40ohm (40) 63*4882a593Smuzhiyun #define LP4_CA_ODT_48ohm (48) 64*4882a593Smuzhiyun #define LP4_CA_ODT_60ohm (60) 65*4882a593Smuzhiyun #define LP4_CA_ODT_80ohm (80) 66*4882a593Smuzhiyun #define LP4_CA_ODT_120ohm (120) 67*4882a593Smuzhiyun #define LP4_CA_ODT_240ohm (240) 68*4882a593Smuzhiyun #define LP4_CA_ODT_DIS (0) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define DDR4_DS_34ohm (34) 71*4882a593Smuzhiyun #define DDR4_DS_48ohm (48) 72*4882a593Smuzhiyun #define DDR4_RTT_NOM_DIS (0) 73*4882a593Smuzhiyun #define DDR4_RTT_NOM_60ohm (60) 74*4882a593Smuzhiyun #define DDR4_RTT_NOM_120ohm (120) 75*4882a593Smuzhiyun #define DDR4_RTT_NOM_40ohm (40) 76*4882a593Smuzhiyun #define DDR4_RTT_NOM_240ohm (240) 77*4882a593Smuzhiyun #define DDR4_RTT_NOM_48ohm (48) 78*4882a593Smuzhiyun #define DDR4_RTT_NOM_80ohm (80) 79*4882a593Smuzhiyun #define DDR4_RTT_NOM_34ohm (34) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define PHY_DDR3_RON_DISABLE (0) 82*4882a593Smuzhiyun #define PHY_DDR3_RON_506ohm (1) 83*4882a593Smuzhiyun #define PHY_DDR3_RON_253ohm (2) 84*4882a593Smuzhiyun #define PHY_DDR3_RON_169hm (3) 85*4882a593Smuzhiyun #define PHY_DDR3_RON_127ohm (4) 86*4882a593Smuzhiyun #define PHY_DDR3_RON_101ohm (5) 87*4882a593Smuzhiyun #define PHY_DDR3_RON_84ohm (6) 88*4882a593Smuzhiyun #define PHY_DDR3_RON_72ohm (7) 89*4882a593Smuzhiyun #define PHY_DDR3_RON_63ohm (16) 90*4882a593Smuzhiyun #define PHY_DDR3_RON_56ohm (17) 91*4882a593Smuzhiyun #define PHY_DDR3_RON_51ohm (18) 92*4882a593Smuzhiyun #define PHY_DDR3_RON_46ohm (19) 93*4882a593Smuzhiyun #define PHY_DDR3_RON_42ohm (20) 94*4882a593Smuzhiyun #define PHY_DDR3_RON_39ohm (21) 95*4882a593Smuzhiyun #define PHY_DDR3_RON_36ohm (22) 96*4882a593Smuzhiyun #define PHY_DDR3_RON_34ohm (23) 97*4882a593Smuzhiyun #define PHY_DDR3_RON_32ohm (24) 98*4882a593Smuzhiyun #define PHY_DDR3_RON_30ohm (25) 99*4882a593Smuzhiyun #define PHY_DDR3_RON_28ohm (26) 100*4882a593Smuzhiyun #define PHY_DDR3_RON_27ohm (27) 101*4882a593Smuzhiyun #define PHY_DDR3_RON_25ohm (28) 102*4882a593Smuzhiyun #define PHY_DDR3_RON_24ohm (29) 103*4882a593Smuzhiyun #define PHY_DDR3_RON_23ohm (30) 104*4882a593Smuzhiyun #define PHY_DDR3_RON_22ohm (31) 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define PHY_DDR3_RTT_DISABLE (0) 107*4882a593Smuzhiyun #define PHY_DDR3_RTT_953ohm (1) 108*4882a593Smuzhiyun #define PHY_DDR3_RTT_483ohm (2) 109*4882a593Smuzhiyun #define PHY_DDR3_RTT_320ohm (3) 110*4882a593Smuzhiyun #define PHY_DDR3_RTT_241ohm (4) 111*4882a593Smuzhiyun #define PHY_DDR3_RTT_193ohm (5) 112*4882a593Smuzhiyun #define PHY_DDR3_RTT_161ohm (6) 113*4882a593Smuzhiyun #define PHY_DDR3_RTT_138ohm (7) 114*4882a593Smuzhiyun #define PHY_DDR3_RTT_121ohm (16) 115*4882a593Smuzhiyun #define PHY_DDR3_RTT_107ohm (17) 116*4882a593Smuzhiyun #define PHY_DDR3_RTT_97ohm (18) 117*4882a593Smuzhiyun #define PHY_DDR3_RTT_88ohm (19) 118*4882a593Smuzhiyun #define PHY_DDR3_RTT_80ohm (20) 119*4882a593Smuzhiyun #define PHY_DDR3_RTT_74ohm (21) 120*4882a593Smuzhiyun #define PHY_DDR3_RTT_69ohm (22) 121*4882a593Smuzhiyun #define PHY_DDR3_RTT_64ohm (23) 122*4882a593Smuzhiyun #define PHY_DDR3_RTT_60ohm (24) 123*4882a593Smuzhiyun #define PHY_DDR3_RTT_57ohm (25) 124*4882a593Smuzhiyun #define PHY_DDR3_RTT_54ohm (26) 125*4882a593Smuzhiyun #define PHY_DDR3_RTT_51ohm (27) 126*4882a593Smuzhiyun #define PHY_DDR3_RTT_48ohm (28) 127*4882a593Smuzhiyun #define PHY_DDR3_RTT_46ohm (29) 128*4882a593Smuzhiyun #define PHY_DDR3_RTT_44ohm (30) 129*4882a593Smuzhiyun #define PHY_DDR3_RTT_42ohm (31) 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_DISABLE (0) 132*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_570ohm (1) 133*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_285ohm (2) 134*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_190ohm (3) 135*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_142ohm (4) 136*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_114ohm (5) 137*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_95ohm (6) 138*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_81ohm (7) 139*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_71ohm (16) 140*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_63ohm (17) 141*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_57ohm (18) 142*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_52ohm (19) 143*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_47ohm (20) 144*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_44ohm (21) 145*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_41ohm (22) 146*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_38ohm (23) 147*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_36ohm (24) 148*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_34ohm (25) 149*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_32ohm (26) 150*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_30ohm (27) 151*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_28ohm (28) 152*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_27ohm (29) 153*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_26ohm (30) 154*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_25ohm (31) 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_DISABLE (0) 157*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_973ohm (1) 158*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_493ohm (2) 159*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_327ohm (3) 160*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_247ohm (4) 161*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_197ohm (5) 162*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_164ohm (6) 163*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_141ohm (7) 164*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_123ohm (16) 165*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_109ohm (17) 166*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_99ohm (18) 167*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_90ohm (19) 168*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_82ohm (20) 169*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_76ohm (21) 170*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_70ohm (22) 171*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_66ohm (23) 172*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_62ohm (24) 173*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_58ohm (25) 174*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_55ohm (26) 175*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_52ohm (27) 176*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_49ohm (28) 177*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_47ohm (29) 178*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_45ohm (30) 179*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RTT_43ohm (31) 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun #define PHY_LPDDR4_RON_DISABLE (0) 182*4882a593Smuzhiyun #define PHY_LPDDR4_RON_606ohm (1) 183*4882a593Smuzhiyun #define PHY_LPDDR4_RON_303ohm (2) 184*4882a593Smuzhiyun #define PHY_LPDDR4_RON_202ohm (3) 185*4882a593Smuzhiyun #define PHY_LPDDR4_RON_152ohm (4) 186*4882a593Smuzhiyun #define PHY_LPDDR4_RON_121ohm (5) 187*4882a593Smuzhiyun #define PHY_LPDDR4_RON_101ohm (6) 188*4882a593Smuzhiyun #define PHY_LPDDR4_RON_87ohm (7) 189*4882a593Smuzhiyun #define PHY_LPDDR4_RON_76ohm (16) 190*4882a593Smuzhiyun #define PHY_LPDDR4_RON_67ohm (17) 191*4882a593Smuzhiyun #define PHY_LPDDR4_RON_61ohm (18) 192*4882a593Smuzhiyun #define PHY_LPDDR4_RON_55ohm (19) 193*4882a593Smuzhiyun #define PHY_LPDDR4_RON_51ohm (20) 194*4882a593Smuzhiyun #define PHY_LPDDR4_RON_47ohm (21) 195*4882a593Smuzhiyun #define PHY_LPDDR4_RON_43ohm (22) 196*4882a593Smuzhiyun #define PHY_LPDDR4_RON_40ohm (23) 197*4882a593Smuzhiyun #define PHY_LPDDR4_RON_38ohm (24) 198*4882a593Smuzhiyun #define PHY_LPDDR4_RON_36ohm (25) 199*4882a593Smuzhiyun #define PHY_LPDDR4_RON_34ohm (26) 200*4882a593Smuzhiyun #define PHY_LPDDR4_RON_32ohm (27) 201*4882a593Smuzhiyun #define PHY_LPDDR4_RON_30ohm (28) 202*4882a593Smuzhiyun #define PHY_LPDDR4_RON_29ohm (29) 203*4882a593Smuzhiyun #define PHY_LPDDR4_RON_28ohm (30) 204*4882a593Smuzhiyun #define PHY_LPDDR4_RON_26ohm (31) 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_DISABLE (0) 207*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_998ohm (1) 208*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_506ohm (2) 209*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_336ohm (3) 210*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_253ohm (4) 211*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_202ohm (5) 212*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_169ohm (6) 213*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_144ohm (7) 214*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_127ohm (16) 215*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_112ohm (17) 216*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_101ohm (18) 217*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_92ohm (19) 218*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_84ohm (20) 219*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_78ohm (21) 220*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_72ohm (22) 221*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_67ohm (23) 222*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_63ohm (24) 223*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_60ohm (25) 224*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_56ohm (26) 225*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_53ohm (27) 226*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_51ohm (28) 227*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_48ohm (29) 228*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_46ohm (30) 229*4882a593Smuzhiyun #define PHY_LPDDR4_RTT_44ohm (31) 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun #endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RV1126_H*/ 232