1*4882a593Smuzhiyun #ifndef DT_BINDINGS_RK3368_DMC_H 2*4882a593Smuzhiyun #define DT_BINDINGS_RK3368_DMC_H 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #define DMC_MSCH_CBDR 0x0 5*4882a593Smuzhiyun #define DMC_MSCH_CBRD 0x1 6*4882a593Smuzhiyun #define DMC_MSCH_CRBD 0x2 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define DDR3_800D 0 9*4882a593Smuzhiyun #define DDR3_800E 1 10*4882a593Smuzhiyun #define DDR3_1066E 2 11*4882a593Smuzhiyun #define DDR3_1066F 3 12*4882a593Smuzhiyun #define DDR3_1066G 4 13*4882a593Smuzhiyun #define DDR3_1333F 5 14*4882a593Smuzhiyun #define DDR3_1333G 6 15*4882a593Smuzhiyun #define DDR3_1333H 7 16*4882a593Smuzhiyun #define DDR3_1333J 8 17*4882a593Smuzhiyun #define DDR3_1600G 9 18*4882a593Smuzhiyun #define DDR3_1600H 10 19*4882a593Smuzhiyun #define DDR3_1600J 11 20*4882a593Smuzhiyun #define DDR3_1600K 12 21*4882a593Smuzhiyun #define DDR3_1866J 13 22*4882a593Smuzhiyun #define DDR3_1866K 14 23*4882a593Smuzhiyun #define DDR3_1866L 15 24*4882a593Smuzhiyun #define DDR3_1866M 16 25*4882a593Smuzhiyun #define DDR3_2133K 17 26*4882a593Smuzhiyun #define DDR3_2133L 18 27*4882a593Smuzhiyun #define DDR3_2133M 19 28*4882a593Smuzhiyun #define DDR3_2133N 20 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #endif 31