1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __ROCKCHIP_MIPI_DSI_H__ 8*4882a593Smuzhiyun #define __ROCKCHIP_MIPI_DSI_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define BIT(nr) (1UL << (nr)) 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* request ACK from peripheral */ 13*4882a593Smuzhiyun #define MIPI_DSI_MSG_REQ_ACK BIT(0) 14*4882a593Smuzhiyun /* use Low Power Mode to transmit message */ 15*4882a593Smuzhiyun #define MIPI_DSI_MSG_USE_LPM BIT(1) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* DSI mode flags */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* video mode */ 20*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO BIT(0) 21*4882a593Smuzhiyun /* video burst mode */ 22*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO_BURST BIT(1) 23*4882a593Smuzhiyun /* video pulse mode */ 24*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO_SYNC_PULSE BIT(2) 25*4882a593Smuzhiyun /* enable auto vertical count mode */ 26*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO_AUTO_VERT BIT(3) 27*4882a593Smuzhiyun /* enable hsync-end packets in vsync-pulse and v-porch area */ 28*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO_HSE BIT(4) 29*4882a593Smuzhiyun /* disable hfront-porch area */ 30*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO_HFP BIT(5) 31*4882a593Smuzhiyun /* disable hback-porch area */ 32*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO_HBP BIT(6) 33*4882a593Smuzhiyun /* disable hsync-active area */ 34*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO_HSA BIT(7) 35*4882a593Smuzhiyun /* flush display FIFO on vsync pulse */ 36*4882a593Smuzhiyun #define MIPI_DSI_MODE_VSYNC_FLUSH BIT(8) 37*4882a593Smuzhiyun /* disable EoT packets in HS mode */ 38*4882a593Smuzhiyun #define MIPI_DSI_MODE_EOT_PACKET BIT(9) 39*4882a593Smuzhiyun /* device supports non-continuous clock behavior (DSI spec 5.6.1) */ 40*4882a593Smuzhiyun #define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10) 41*4882a593Smuzhiyun /* transmit data in low power */ 42*4882a593Smuzhiyun #define MIPI_DSI_MODE_LPM BIT(11) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define MIPI_DSI_DCS_POWER_MODE_DISPLAY BIT(2) 45*4882a593Smuzhiyun #define MIPI_DSI_DCS_POWER_MODE_NORMAL BIT(3) 46*4882a593Smuzhiyun #define MIPI_DSI_DCS_POWER_MODE_SLEEP BIT(4) 47*4882a593Smuzhiyun #define MIPI_DSI_DCS_POWER_MODE_PARTIAL BIT(5) 48*4882a593Smuzhiyun #define MIPI_DSI_DCS_POWER_MODE_IDLE BIT(6) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define MIPI_DSI_FMT_RGB888 0 51*4882a593Smuzhiyun #define MIPI_DSI_FMT_RGB666 1 52*4882a593Smuzhiyun #define MIPI_DSI_FMT_RGB666_PACKED 2 53*4882a593Smuzhiyun #define MIPI_DSI_FMT_RGB565 3 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #endif /* __ROCKCHIP_MIPI_DSI__ */ 56