1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2016, NVIDIA CORPORATION. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This header provides constants for binding nvidia,tegra186-gpio*. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below 9*4882a593Smuzhiyun * provide names for this. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The second cell contains standard flag values specified in gpio.h. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef _DT_BINDINGS_GPIO_TEGRA186_GPIO_H 15*4882a593Smuzhiyun #define _DT_BINDINGS_GPIO_TEGRA186_GPIO_H 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include <dt-bindings/gpio/gpio.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* GPIOs implemented by main GPIO controller */ 20*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO_PORT_A 0 21*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO_PORT_B 1 22*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO_PORT_C 2 23*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO_PORT_D 3 24*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO_PORT_E 4 25*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO_PORT_F 5 26*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO_PORT_G 6 27*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO_PORT_H 7 28*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO_PORT_I 8 29*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO_PORT_J 9 30*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO_PORT_K 10 31*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO_PORT_L 11 32*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO_PORT_M 12 33*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO_PORT_N 13 34*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO_PORT_O 14 35*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO_PORT_P 15 36*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO_PORT_Q 16 37*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO_PORT_R 17 38*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO_PORT_T 18 39*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO_PORT_X 19 40*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO_PORT_Y 20 41*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO_PORT_BB 21 42*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO_PORT_CC 22 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define TEGRA_MAIN_GPIO(port, offset) \ 45*4882a593Smuzhiyun ((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* GPIOs implemented by AON GPIO controller */ 48*4882a593Smuzhiyun #define TEGRA_AON_GPIO_PORT_S 0 49*4882a593Smuzhiyun #define TEGRA_AON_GPIO_PORT_U 1 50*4882a593Smuzhiyun #define TEGRA_AON_GPIO_PORT_V 2 51*4882a593Smuzhiyun #define TEGRA_AON_GPIO_PORT_W 3 52*4882a593Smuzhiyun #define TEGRA_AON_GPIO_PORT_Z 4 53*4882a593Smuzhiyun #define TEGRA_AON_GPIO_PORT_AA 5 54*4882a593Smuzhiyun #define TEGRA_AON_GPIO_PORT_EE 6 55*4882a593Smuzhiyun #define TEGRA_AON_GPIO_PORT_FF 7 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define TEGRA_AON_GPIO(port, offset) \ 58*4882a593Smuzhiyun ((TEGRA_AON_GPIO_PORT_##port * 8) + offset) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #endif 61