1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This header provides macros for at91 dma bindings. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2013 Ludovic Desroches <ludovic.desroches@atmel.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * GPLv2 only 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __DT_BINDINGS_AT91_DMA_H__ 10*4882a593Smuzhiyun #define __DT_BINDINGS_AT91_DMA_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* ---------- HDMAC ---------- */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * Source and/or destination peripheral ID 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun #define AT91_DMA_CFG_PER_ID_MASK (0xff) 18*4882a593Smuzhiyun #define AT91_DMA_CFG_PER_ID(id) (id & AT91_DMA_CFG_PER_ID_MASK) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun * FIFO configuration: it defines when a request is serviced. 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun #define AT91_DMA_CFG_FIFOCFG_OFFSET (8) 24*4882a593Smuzhiyun #define AT91_DMA_CFG_FIFOCFG_MASK (0xf << AT91_DMA_CFG_FIFOCFG_OFFSET) 25*4882a593Smuzhiyun #define AT91_DMA_CFG_FIFOCFG_HALF (0x0 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* half FIFO (default behavior) */ 26*4882a593Smuzhiyun #define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */ 27*4882a593Smuzhiyun #define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* ---------- XDMAC ---------- */ 31*4882a593Smuzhiyun #define AT91_XDMAC_DT_MEM_IF_MASK (0x1) 32*4882a593Smuzhiyun #define AT91_XDMAC_DT_MEM_IF_OFFSET (13) 33*4882a593Smuzhiyun #define AT91_XDMAC_DT_MEM_IF(mem_if) (((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \ 34*4882a593Smuzhiyun << AT91_XDMAC_DT_MEM_IF_OFFSET) 35*4882a593Smuzhiyun #define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \ 36*4882a593Smuzhiyun & AT91_XDMAC_DT_MEM_IF_MASK) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define AT91_XDMAC_DT_PER_IF_MASK (0x1) 39*4882a593Smuzhiyun #define AT91_XDMAC_DT_PER_IF_OFFSET (14) 40*4882a593Smuzhiyun #define AT91_XDMAC_DT_PER_IF(per_if) (((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \ 41*4882a593Smuzhiyun << AT91_XDMAC_DT_PER_IF_OFFSET) 42*4882a593Smuzhiyun #define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \ 43*4882a593Smuzhiyun & AT91_XDMAC_DT_PER_IF_MASK) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define AT91_XDMAC_DT_PERID_MASK (0x7f) 46*4882a593Smuzhiyun #define AT91_XDMAC_DT_PERID_OFFSET (24) 47*4882a593Smuzhiyun #define AT91_XDMAC_DT_PERID(perid) (((perid) & AT91_XDMAC_DT_PERID_MASK) \ 48*4882a593Smuzhiyun << AT91_XDMAC_DT_PERID_OFFSET) 49*4882a593Smuzhiyun #define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \ 50*4882a593Smuzhiyun & AT91_XDMAC_DT_PERID_MASK) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #endif /* __DT_BINDINGS_AT91_DMA_H__ */ 53