1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015-2016 Marvell International Ltd. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _COMPHY_DATA_H_ 8*4882a593Smuzhiyun #define _COMPHY_DATA_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define PHY_SPEED_1_25G 0 11*4882a593Smuzhiyun #define PHY_SPEED_1_5G 1 12*4882a593Smuzhiyun #define PHY_SPEED_2_5G 2 13*4882a593Smuzhiyun #define PHY_SPEED_3G 3 14*4882a593Smuzhiyun #define PHY_SPEED_3_125G 4 15*4882a593Smuzhiyun #define PHY_SPEED_5G 5 16*4882a593Smuzhiyun #define PHY_SPEED_5_15625G 6 17*4882a593Smuzhiyun #define PHY_SPEED_6G 7 18*4882a593Smuzhiyun #define PHY_SPEED_6_25G 8 19*4882a593Smuzhiyun #define PHY_SPEED_10_3125G 9 20*4882a593Smuzhiyun #define PHY_SPEED_MAX 10 21*4882a593Smuzhiyun #define PHY_SPEED_INVALID 0xff 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define PHY_TYPE_UNCONNECTED 0 24*4882a593Smuzhiyun #define PHY_TYPE_PEX0 1 25*4882a593Smuzhiyun #define PHY_TYPE_PEX1 2 26*4882a593Smuzhiyun #define PHY_TYPE_PEX2 3 27*4882a593Smuzhiyun #define PHY_TYPE_PEX3 4 28*4882a593Smuzhiyun #define PHY_TYPE_SATA0 5 29*4882a593Smuzhiyun #define PHY_TYPE_SATA1 6 30*4882a593Smuzhiyun #define PHY_TYPE_SATA2 7 31*4882a593Smuzhiyun #define PHY_TYPE_SATA3 8 32*4882a593Smuzhiyun #define PHY_TYPE_SGMII0 9 33*4882a593Smuzhiyun #define PHY_TYPE_SGMII1 10 34*4882a593Smuzhiyun #define PHY_TYPE_SGMII2 11 35*4882a593Smuzhiyun #define PHY_TYPE_SGMII3 12 36*4882a593Smuzhiyun #define PHY_TYPE_QSGMII 13 37*4882a593Smuzhiyun #define PHY_TYPE_USB3_HOST0 14 38*4882a593Smuzhiyun #define PHY_TYPE_USB3_HOST1 15 39*4882a593Smuzhiyun #define PHY_TYPE_USB3_DEVICE 16 40*4882a593Smuzhiyun #define PHY_TYPE_XAUI0 17 41*4882a593Smuzhiyun #define PHY_TYPE_XAUI1 18 42*4882a593Smuzhiyun #define PHY_TYPE_XAUI2 19 43*4882a593Smuzhiyun #define PHY_TYPE_XAUI3 20 44*4882a593Smuzhiyun #define PHY_TYPE_RXAUI0 21 45*4882a593Smuzhiyun #define PHY_TYPE_RXAUI1 22 46*4882a593Smuzhiyun #define PHY_TYPE_SFI 23 47*4882a593Smuzhiyun #define PHY_TYPE_IGNORE 24 48*4882a593Smuzhiyun #define PHY_TYPE_MAX 25 49*4882a593Smuzhiyun #define PHY_TYPE_INVALID 0xff 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define PHY_POLARITY_NO_INVERT 0 52*4882a593Smuzhiyun #define PHY_POLARITY_TXD_INVERT 1 53*4882a593Smuzhiyun #define PHY_POLARITY_RXD_INVERT 2 54*4882a593Smuzhiyun #define PHY_POLARITY_ALL_INVERT \ 55*4882a593Smuzhiyun (PHY_POLARITY_TXD_INVERT | PHY_POLARITY_RXD_INVERT) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define UTMI_PHY_TO_USB3_HOST0 0 58*4882a593Smuzhiyun #define UTMI_PHY_TO_USB3_HOST1 1 59*4882a593Smuzhiyun #define UTMI_PHY_TO_USB3_DEVICE0 2 60*4882a593Smuzhiyun #define UTMI_PHY_INVALID 0xff 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #endif /* _COMPHY_DATA_H_ */ 63*4882a593Smuzhiyun 64