1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This header provides constants for binding nvidia,tegra30-car. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 5*4882a593Smuzhiyun * registers. These IDs often match those in the CAR's RST_DEVICES registers, 6*4882a593Smuzhiyun * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 7*4882a593Smuzhiyun * this case, those clocks are assigned IDs above 160 in order to highlight 8*4882a593Smuzhiyun * this issue. Implementations that interpret these clock IDs as bit values 9*4882a593Smuzhiyun * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 10*4882a593Smuzhiyun * explicitly handle these special cases. 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * The balance of the clocks controlled by the CAR are assigned IDs of 160 and 13*4882a593Smuzhiyun * above. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H 17*4882a593Smuzhiyun #define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define TEGRA30_CLK_CPU 0 20*4882a593Smuzhiyun /* 1 */ 21*4882a593Smuzhiyun /* 2 */ 22*4882a593Smuzhiyun /* 3 */ 23*4882a593Smuzhiyun #define TEGRA30_CLK_RTC 4 24*4882a593Smuzhiyun #define TEGRA30_CLK_TIMER 5 25*4882a593Smuzhiyun #define TEGRA30_CLK_UARTA 6 26*4882a593Smuzhiyun /* 7 (register bit affects uartb and vfir) */ 27*4882a593Smuzhiyun #define TEGRA30_CLK_GPIO 8 28*4882a593Smuzhiyun #define TEGRA30_CLK_SDMMC2 9 29*4882a593Smuzhiyun /* 10 (register bit affects spdif_in and spdif_out) */ 30*4882a593Smuzhiyun #define TEGRA30_CLK_I2S1 11 31*4882a593Smuzhiyun #define TEGRA30_CLK_I2C1 12 32*4882a593Smuzhiyun #define TEGRA30_CLK_NDFLASH 13 33*4882a593Smuzhiyun #define TEGRA30_CLK_SDMMC1 14 34*4882a593Smuzhiyun #define TEGRA30_CLK_SDMMC4 15 35*4882a593Smuzhiyun /* 16 */ 36*4882a593Smuzhiyun #define TEGRA30_CLK_PWM 17 37*4882a593Smuzhiyun #define TEGRA30_CLK_I2S2 18 38*4882a593Smuzhiyun #define TEGRA30_CLK_EPP 19 39*4882a593Smuzhiyun /* 20 (register bit affects vi and vi_sensor) */ 40*4882a593Smuzhiyun #define TEGRA30_CLK_GR2D 21 41*4882a593Smuzhiyun #define TEGRA30_CLK_USBD 22 42*4882a593Smuzhiyun #define TEGRA30_CLK_ISP 23 43*4882a593Smuzhiyun #define TEGRA30_CLK_GR3D 24 44*4882a593Smuzhiyun /* 25 */ 45*4882a593Smuzhiyun #define TEGRA30_CLK_DISP2 26 46*4882a593Smuzhiyun #define TEGRA30_CLK_DISP1 27 47*4882a593Smuzhiyun #define TEGRA30_CLK_HOST1X 28 48*4882a593Smuzhiyun #define TEGRA30_CLK_VCP 29 49*4882a593Smuzhiyun #define TEGRA30_CLK_I2S0 30 50*4882a593Smuzhiyun #define TEGRA30_CLK_COP_CACHE 31 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define TEGRA30_CLK_MC 32 53*4882a593Smuzhiyun #define TEGRA30_CLK_AHBDMA 33 54*4882a593Smuzhiyun #define TEGRA30_CLK_APBDMA 34 55*4882a593Smuzhiyun /* 35 */ 56*4882a593Smuzhiyun #define TEGRA30_CLK_KBC 36 57*4882a593Smuzhiyun #define TEGRA30_CLK_STATMON 37 58*4882a593Smuzhiyun #define TEGRA30_CLK_PMC 38 59*4882a593Smuzhiyun /* 39 (register bit affects fuse and fuse_burn) */ 60*4882a593Smuzhiyun #define TEGRA30_CLK_KFUSE 40 61*4882a593Smuzhiyun #define TEGRA30_CLK_SBC1 41 62*4882a593Smuzhiyun #define TEGRA30_CLK_NOR 42 63*4882a593Smuzhiyun /* 43 */ 64*4882a593Smuzhiyun #define TEGRA30_CLK_SBC2 44 65*4882a593Smuzhiyun /* 45 */ 66*4882a593Smuzhiyun #define TEGRA30_CLK_SBC3 46 67*4882a593Smuzhiyun #define TEGRA30_CLK_I2C5 47 68*4882a593Smuzhiyun #define TEGRA30_CLK_DSIA 48 69*4882a593Smuzhiyun /* 49 (register bit affects cve and tvo) */ 70*4882a593Smuzhiyun #define TEGRA30_CLK_MIPI 50 71*4882a593Smuzhiyun #define TEGRA30_CLK_HDMI 51 72*4882a593Smuzhiyun #define TEGRA30_CLK_CSI 52 73*4882a593Smuzhiyun #define TEGRA30_CLK_TVDAC 53 74*4882a593Smuzhiyun #define TEGRA30_CLK_I2C2 54 75*4882a593Smuzhiyun #define TEGRA30_CLK_UARTC 55 76*4882a593Smuzhiyun /* 56 */ 77*4882a593Smuzhiyun #define TEGRA30_CLK_EMC 57 78*4882a593Smuzhiyun #define TEGRA30_CLK_USB2 58 79*4882a593Smuzhiyun #define TEGRA30_CLK_USB3 59 80*4882a593Smuzhiyun #define TEGRA30_CLK_MPE 60 81*4882a593Smuzhiyun #define TEGRA30_CLK_VDE 61 82*4882a593Smuzhiyun #define TEGRA30_CLK_BSEA 62 83*4882a593Smuzhiyun #define TEGRA30_CLK_BSEV 63 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define TEGRA30_CLK_SPEEDO 64 86*4882a593Smuzhiyun #define TEGRA30_CLK_UARTD 65 87*4882a593Smuzhiyun #define TEGRA30_CLK_UARTE 66 88*4882a593Smuzhiyun #define TEGRA30_CLK_I2C3 67 89*4882a593Smuzhiyun #define TEGRA30_CLK_SBC4 68 90*4882a593Smuzhiyun #define TEGRA30_CLK_SDMMC3 69 91*4882a593Smuzhiyun #define TEGRA30_CLK_PCIE 70 92*4882a593Smuzhiyun #define TEGRA30_CLK_OWR 71 93*4882a593Smuzhiyun #define TEGRA30_CLK_AFI 72 94*4882a593Smuzhiyun #define TEGRA30_CLK_CSITE 73 95*4882a593Smuzhiyun /* 74 */ 96*4882a593Smuzhiyun #define TEGRA30_CLK_AVPUCQ 75 97*4882a593Smuzhiyun #define TEGRA30_CLK_LA 76 98*4882a593Smuzhiyun /* 77 */ 99*4882a593Smuzhiyun /* 78 */ 100*4882a593Smuzhiyun #define TEGRA30_CLK_DTV 79 101*4882a593Smuzhiyun #define TEGRA30_CLK_NDSPEED 80 102*4882a593Smuzhiyun #define TEGRA30_CLK_I2CSLOW 81 103*4882a593Smuzhiyun #define TEGRA30_CLK_DSIB 82 104*4882a593Smuzhiyun /* 83 */ 105*4882a593Smuzhiyun #define TEGRA30_CLK_IRAMA 84 106*4882a593Smuzhiyun #define TEGRA30_CLK_IRAMB 85 107*4882a593Smuzhiyun #define TEGRA30_CLK_IRAMC 86 108*4882a593Smuzhiyun #define TEGRA30_CLK_IRAMD 87 109*4882a593Smuzhiyun #define TEGRA30_CLK_CRAM2 88 110*4882a593Smuzhiyun /* 89 */ 111*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */ 112*4882a593Smuzhiyun /* 91 */ 113*4882a593Smuzhiyun #define TEGRA30_CLK_CSUS 92 114*4882a593Smuzhiyun #define TEGRA30_CLK_CDEV2 93 115*4882a593Smuzhiyun #define TEGRA30_CLK_CDEV1 94 116*4882a593Smuzhiyun /* 95 */ 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define TEGRA30_CLK_CPU_G 96 119*4882a593Smuzhiyun #define TEGRA30_CLK_CPU_LP 97 120*4882a593Smuzhiyun #define TEGRA30_CLK_GR3D2 98 121*4882a593Smuzhiyun #define TEGRA30_CLK_MSELECT 99 122*4882a593Smuzhiyun #define TEGRA30_CLK_TSENSOR 100 123*4882a593Smuzhiyun #define TEGRA30_CLK_I2S3 101 124*4882a593Smuzhiyun #define TEGRA30_CLK_I2S4 102 125*4882a593Smuzhiyun #define TEGRA30_CLK_I2C4 103 126*4882a593Smuzhiyun #define TEGRA30_CLK_SBC5 104 127*4882a593Smuzhiyun #define TEGRA30_CLK_SBC6 105 128*4882a593Smuzhiyun #define TEGRA30_CLK_D_AUDIO 106 129*4882a593Smuzhiyun #define TEGRA30_CLK_APBIF 107 130*4882a593Smuzhiyun #define TEGRA30_CLK_DAM0 108 131*4882a593Smuzhiyun #define TEGRA30_CLK_DAM1 109 132*4882a593Smuzhiyun #define TEGRA30_CLK_DAM2 110 133*4882a593Smuzhiyun #define TEGRA30_CLK_HDA2CODEC_2X 111 134*4882a593Smuzhiyun #define TEGRA30_CLK_ATOMICS 112 135*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO0_2X 113 136*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO1_2X 114 137*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO2_2X 115 138*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO3_2X 116 139*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO4_2X 117 140*4882a593Smuzhiyun #define TEGRA30_CLK_SPDIF_2X 118 141*4882a593Smuzhiyun #define TEGRA30_CLK_ACTMON 119 142*4882a593Smuzhiyun #define TEGRA30_CLK_EXTERN1 120 143*4882a593Smuzhiyun #define TEGRA30_CLK_EXTERN2 121 144*4882a593Smuzhiyun #define TEGRA30_CLK_EXTERN3 122 145*4882a593Smuzhiyun #define TEGRA30_CLK_SATA_OOB 123 146*4882a593Smuzhiyun #define TEGRA30_CLK_SATA 124 147*4882a593Smuzhiyun #define TEGRA30_CLK_HDA 125 148*4882a593Smuzhiyun /* 126 */ 149*4882a593Smuzhiyun #define TEGRA30_CLK_SE 127 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #define TEGRA30_CLK_HDA2HDMI 128 152*4882a593Smuzhiyun #define TEGRA30_CLK_SATA_COLD 129 153*4882a593Smuzhiyun /* 130 */ 154*4882a593Smuzhiyun /* 131 */ 155*4882a593Smuzhiyun /* 132 */ 156*4882a593Smuzhiyun /* 133 */ 157*4882a593Smuzhiyun /* 134 */ 158*4882a593Smuzhiyun /* 135 */ 159*4882a593Smuzhiyun /* 136 */ 160*4882a593Smuzhiyun /* 137 */ 161*4882a593Smuzhiyun /* 138 */ 162*4882a593Smuzhiyun /* 139 */ 163*4882a593Smuzhiyun /* 140 */ 164*4882a593Smuzhiyun /* 141 */ 165*4882a593Smuzhiyun /* 142 */ 166*4882a593Smuzhiyun /* 143 */ 167*4882a593Smuzhiyun /* 144 */ 168*4882a593Smuzhiyun /* 145 */ 169*4882a593Smuzhiyun /* 146 */ 170*4882a593Smuzhiyun /* 147 */ 171*4882a593Smuzhiyun /* 148 */ 172*4882a593Smuzhiyun /* 149 */ 173*4882a593Smuzhiyun /* 150 */ 174*4882a593Smuzhiyun /* 151 */ 175*4882a593Smuzhiyun /* 152 */ 176*4882a593Smuzhiyun /* 153 */ 177*4882a593Smuzhiyun /* 154 */ 178*4882a593Smuzhiyun /* 155 */ 179*4882a593Smuzhiyun /* 156 */ 180*4882a593Smuzhiyun /* 157 */ 181*4882a593Smuzhiyun /* 158 */ 182*4882a593Smuzhiyun /* 159 */ 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun #define TEGRA30_CLK_UARTB 160 185*4882a593Smuzhiyun #define TEGRA30_CLK_VFIR 161 186*4882a593Smuzhiyun #define TEGRA30_CLK_SPDIF_IN 162 187*4882a593Smuzhiyun #define TEGRA30_CLK_SPDIF_OUT 163 188*4882a593Smuzhiyun #define TEGRA30_CLK_VI 164 189*4882a593Smuzhiyun #define TEGRA30_CLK_VI_SENSOR 165 190*4882a593Smuzhiyun #define TEGRA30_CLK_FUSE 166 191*4882a593Smuzhiyun #define TEGRA30_CLK_FUSE_BURN 167 192*4882a593Smuzhiyun #define TEGRA30_CLK_CVE 168 193*4882a593Smuzhiyun #define TEGRA30_CLK_TVO 169 194*4882a593Smuzhiyun #define TEGRA30_CLK_CLK_32K 170 195*4882a593Smuzhiyun #define TEGRA30_CLK_CLK_M 171 196*4882a593Smuzhiyun #define TEGRA30_CLK_CLK_M_DIV2 172 197*4882a593Smuzhiyun #define TEGRA30_CLK_CLK_M_DIV4 173 198*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_REF 174 199*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_C 175 200*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_C_OUT1 176 201*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_M 177 202*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_M_OUT1 178 203*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_P 179 204*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_P_OUT1 180 205*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_P_OUT2 181 206*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_P_OUT3 182 207*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_P_OUT4 183 208*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_A 184 209*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_A_OUT0 185 210*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_D 186 211*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_D_OUT0 187 212*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_D2 188 213*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_D2_OUT0 189 214*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_U 190 215*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_X 191 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_X_OUT0 192 218*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_E 193 219*4882a593Smuzhiyun #define TEGRA30_CLK_SPDIF_IN_SYNC 194 220*4882a593Smuzhiyun #define TEGRA30_CLK_I2S0_SYNC 195 221*4882a593Smuzhiyun #define TEGRA30_CLK_I2S1_SYNC 196 222*4882a593Smuzhiyun #define TEGRA30_CLK_I2S2_SYNC 197 223*4882a593Smuzhiyun #define TEGRA30_CLK_I2S3_SYNC 198 224*4882a593Smuzhiyun #define TEGRA30_CLK_I2S4_SYNC 199 225*4882a593Smuzhiyun #define TEGRA30_CLK_VIMCLK_SYNC 200 226*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO0 201 227*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO1 202 228*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO2 203 229*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO3 204 230*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO4 205 231*4882a593Smuzhiyun #define TEGRA30_CLK_SPDIF 206 232*4882a593Smuzhiyun #define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */ 233*4882a593Smuzhiyun #define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */ 234*4882a593Smuzhiyun #define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */ 235*4882a593Smuzhiyun #define TEGRA30_CLK_SCLK 210 236*4882a593Smuzhiyun #define TEGRA30_CLK_BLINK 211 237*4882a593Smuzhiyun #define TEGRA30_CLK_CCLK_G 212 238*4882a593Smuzhiyun #define TEGRA30_CLK_CCLK_LP 213 239*4882a593Smuzhiyun #define TEGRA30_CLK_TWD 214 240*4882a593Smuzhiyun #define TEGRA30_CLK_CML0 215 241*4882a593Smuzhiyun #define TEGRA30_CLK_CML1 216 242*4882a593Smuzhiyun #define TEGRA30_CLK_HCLK 217 243*4882a593Smuzhiyun #define TEGRA30_CLK_PCLK 218 244*4882a593Smuzhiyun /* 219 */ 245*4882a593Smuzhiyun /* 220 */ 246*4882a593Smuzhiyun /* 221 */ 247*4882a593Smuzhiyun /* 222 */ 248*4882a593Smuzhiyun /* 223 */ 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun /* 288 */ 251*4882a593Smuzhiyun /* 289 */ 252*4882a593Smuzhiyun /* 290 */ 253*4882a593Smuzhiyun /* 291 */ 254*4882a593Smuzhiyun /* 292 */ 255*4882a593Smuzhiyun /* 293 */ 256*4882a593Smuzhiyun /* 294 */ 257*4882a593Smuzhiyun /* 295 */ 258*4882a593Smuzhiyun /* 296 */ 259*4882a593Smuzhiyun /* 297 */ 260*4882a593Smuzhiyun /* 298 */ 261*4882a593Smuzhiyun /* 299 */ 262*4882a593Smuzhiyun #define TEGRA30_CLK_CLK_OUT_1_MUX 300 263*4882a593Smuzhiyun #define TEGRA30_CLK_CLK_OUT_2_MUX 301 264*4882a593Smuzhiyun #define TEGRA30_CLK_CLK_OUT_3_MUX 302 265*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO0_MUX 303 266*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO1_MUX 304 267*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO2_MUX 305 268*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO3_MUX 306 269*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO4_MUX 307 270*4882a593Smuzhiyun #define TEGRA30_CLK_SPDIF_MUX 308 271*4882a593Smuzhiyun #define TEGRA30_CLK_CLK_MAX 309 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */ 274