1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This header provides constants for binding nvidia,tegra124-car or 3*4882a593Smuzhiyun * nvidia,tegra132-car. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 6*4882a593Smuzhiyun * registers. These IDs often match those in the CAR's RST_DEVICES registers, 7*4882a593Smuzhiyun * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 8*4882a593Smuzhiyun * this case, those clocks are assigned IDs above 185 in order to highlight 9*4882a593Smuzhiyun * this issue. Implementations that interpret these clock IDs as bit values 10*4882a593Smuzhiyun * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 11*4882a593Smuzhiyun * explicitly handle these special cases. 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * The balance of the clocks controlled by the CAR are assigned IDs of 185 and 14*4882a593Smuzhiyun * above. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H 18*4882a593Smuzhiyun #define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 0 */ 21*4882a593Smuzhiyun /* 1 */ 22*4882a593Smuzhiyun /* 2 */ 23*4882a593Smuzhiyun #define TEGRA124_CLK_ISPB 3 24*4882a593Smuzhiyun #define TEGRA124_CLK_RTC 4 25*4882a593Smuzhiyun #define TEGRA124_CLK_TIMER 5 26*4882a593Smuzhiyun #define TEGRA124_CLK_UARTA 6 27*4882a593Smuzhiyun /* 7 (register bit affects uartb and vfir) */ 28*4882a593Smuzhiyun /* 8 */ 29*4882a593Smuzhiyun #define TEGRA124_CLK_SDMMC2 9 30*4882a593Smuzhiyun /* 10 (register bit affects spdif_in and spdif_out) */ 31*4882a593Smuzhiyun #define TEGRA124_CLK_I2S1 11 32*4882a593Smuzhiyun #define TEGRA124_CLK_I2C1 12 33*4882a593Smuzhiyun /* 13 */ 34*4882a593Smuzhiyun #define TEGRA124_CLK_SDMMC1 14 35*4882a593Smuzhiyun #define TEGRA124_CLK_SDMMC4 15 36*4882a593Smuzhiyun /* 16 */ 37*4882a593Smuzhiyun #define TEGRA124_CLK_PWM 17 38*4882a593Smuzhiyun #define TEGRA124_CLK_I2S2 18 39*4882a593Smuzhiyun /* 20 (register bit affects vi and vi_sensor) */ 40*4882a593Smuzhiyun /* 21 */ 41*4882a593Smuzhiyun #define TEGRA124_CLK_USBD 22 42*4882a593Smuzhiyun #define TEGRA124_CLK_ISP 23 43*4882a593Smuzhiyun /* 26 */ 44*4882a593Smuzhiyun /* 25 */ 45*4882a593Smuzhiyun #define TEGRA124_CLK_DISP2 26 46*4882a593Smuzhiyun #define TEGRA124_CLK_DISP1 27 47*4882a593Smuzhiyun #define TEGRA124_CLK_HOST1X 28 48*4882a593Smuzhiyun #define TEGRA124_CLK_VCP 29 49*4882a593Smuzhiyun #define TEGRA124_CLK_I2S0 30 50*4882a593Smuzhiyun /* 31 */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define TEGRA124_CLK_MC 32 53*4882a593Smuzhiyun /* 33 */ 54*4882a593Smuzhiyun #define TEGRA124_CLK_APBDMA 34 55*4882a593Smuzhiyun /* 35 */ 56*4882a593Smuzhiyun #define TEGRA124_CLK_KBC 36 57*4882a593Smuzhiyun /* 37 */ 58*4882a593Smuzhiyun /* 38 */ 59*4882a593Smuzhiyun /* 39 (register bit affects fuse and fuse_burn) */ 60*4882a593Smuzhiyun #define TEGRA124_CLK_KFUSE 40 61*4882a593Smuzhiyun #define TEGRA124_CLK_SBC1 41 62*4882a593Smuzhiyun #define TEGRA124_CLK_NOR 42 63*4882a593Smuzhiyun /* 43 */ 64*4882a593Smuzhiyun #define TEGRA124_CLK_SBC2 44 65*4882a593Smuzhiyun /* 45 */ 66*4882a593Smuzhiyun #define TEGRA124_CLK_SBC3 46 67*4882a593Smuzhiyun #define TEGRA124_CLK_I2C5 47 68*4882a593Smuzhiyun #define TEGRA124_CLK_DSIA 48 69*4882a593Smuzhiyun /* 49 */ 70*4882a593Smuzhiyun #define TEGRA124_CLK_MIPI 50 71*4882a593Smuzhiyun #define TEGRA124_CLK_HDMI 51 72*4882a593Smuzhiyun #define TEGRA124_CLK_CSI 52 73*4882a593Smuzhiyun /* 53 */ 74*4882a593Smuzhiyun #define TEGRA124_CLK_I2C2 54 75*4882a593Smuzhiyun #define TEGRA124_CLK_UARTC 55 76*4882a593Smuzhiyun #define TEGRA124_CLK_MIPI_CAL 56 77*4882a593Smuzhiyun #define TEGRA124_CLK_EMC 57 78*4882a593Smuzhiyun #define TEGRA124_CLK_USB2 58 79*4882a593Smuzhiyun #define TEGRA124_CLK_USB3 59 80*4882a593Smuzhiyun /* 60 */ 81*4882a593Smuzhiyun #define TEGRA124_CLK_VDE 61 82*4882a593Smuzhiyun #define TEGRA124_CLK_BSEA 62 83*4882a593Smuzhiyun #define TEGRA124_CLK_BSEV 63 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* 64 */ 86*4882a593Smuzhiyun #define TEGRA124_CLK_UARTD 65 87*4882a593Smuzhiyun /* 66 */ 88*4882a593Smuzhiyun #define TEGRA124_CLK_I2C3 67 89*4882a593Smuzhiyun #define TEGRA124_CLK_SBC4 68 90*4882a593Smuzhiyun #define TEGRA124_CLK_SDMMC3 69 91*4882a593Smuzhiyun #define TEGRA124_CLK_PCIE 70 92*4882a593Smuzhiyun #define TEGRA124_CLK_OWR 71 93*4882a593Smuzhiyun #define TEGRA124_CLK_AFI 72 94*4882a593Smuzhiyun #define TEGRA124_CLK_CSITE 73 95*4882a593Smuzhiyun /* 74 */ 96*4882a593Smuzhiyun /* 75 */ 97*4882a593Smuzhiyun #define TEGRA124_CLK_LA 76 98*4882a593Smuzhiyun #define TEGRA124_CLK_TRACE 77 99*4882a593Smuzhiyun #define TEGRA124_CLK_SOC_THERM 78 100*4882a593Smuzhiyun #define TEGRA124_CLK_DTV 79 101*4882a593Smuzhiyun /* 80 */ 102*4882a593Smuzhiyun #define TEGRA124_CLK_I2CSLOW 81 103*4882a593Smuzhiyun #define TEGRA124_CLK_DSIB 82 104*4882a593Smuzhiyun #define TEGRA124_CLK_TSEC 83 105*4882a593Smuzhiyun /* 84 */ 106*4882a593Smuzhiyun /* 85 */ 107*4882a593Smuzhiyun /* 86 */ 108*4882a593Smuzhiyun /* 87 */ 109*4882a593Smuzhiyun /* 88 */ 110*4882a593Smuzhiyun #define TEGRA124_CLK_XUSB_HOST 89 111*4882a593Smuzhiyun /* 90 */ 112*4882a593Smuzhiyun #define TEGRA124_CLK_MSENC 91 113*4882a593Smuzhiyun #define TEGRA124_CLK_CSUS 92 114*4882a593Smuzhiyun /* 93 */ 115*4882a593Smuzhiyun /* 94 */ 116*4882a593Smuzhiyun /* 95 (bit affects xusb_dev and xusb_dev_src) */ 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* 96 */ 119*4882a593Smuzhiyun /* 97 */ 120*4882a593Smuzhiyun /* 98 */ 121*4882a593Smuzhiyun #define TEGRA124_CLK_MSELECT 99 122*4882a593Smuzhiyun #define TEGRA124_CLK_TSENSOR 100 123*4882a593Smuzhiyun #define TEGRA124_CLK_I2S3 101 124*4882a593Smuzhiyun #define TEGRA124_CLK_I2S4 102 125*4882a593Smuzhiyun #define TEGRA124_CLK_I2C4 103 126*4882a593Smuzhiyun #define TEGRA124_CLK_SBC5 104 127*4882a593Smuzhiyun #define TEGRA124_CLK_SBC6 105 128*4882a593Smuzhiyun #define TEGRA124_CLK_D_AUDIO 106 129*4882a593Smuzhiyun #define TEGRA124_CLK_APBIF 107 130*4882a593Smuzhiyun #define TEGRA124_CLK_DAM0 108 131*4882a593Smuzhiyun #define TEGRA124_CLK_DAM1 109 132*4882a593Smuzhiyun #define TEGRA124_CLK_DAM2 110 133*4882a593Smuzhiyun #define TEGRA124_CLK_HDA2CODEC_2X 111 134*4882a593Smuzhiyun /* 112 */ 135*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO0_2X 113 136*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO1_2X 114 137*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO2_2X 115 138*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO3_2X 116 139*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO4_2X 117 140*4882a593Smuzhiyun #define TEGRA124_CLK_SPDIF_2X 118 141*4882a593Smuzhiyun #define TEGRA124_CLK_ACTMON 119 142*4882a593Smuzhiyun #define TEGRA124_CLK_EXTERN1 120 143*4882a593Smuzhiyun #define TEGRA124_CLK_EXTERN2 121 144*4882a593Smuzhiyun #define TEGRA124_CLK_EXTERN3 122 145*4882a593Smuzhiyun #define TEGRA124_CLK_SATA_OOB 123 146*4882a593Smuzhiyun #define TEGRA124_CLK_SATA 124 147*4882a593Smuzhiyun #define TEGRA124_CLK_HDA 125 148*4882a593Smuzhiyun /* 126 */ 149*4882a593Smuzhiyun #define TEGRA124_CLK_SE 127 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #define TEGRA124_CLK_HDA2HDMI 128 152*4882a593Smuzhiyun #define TEGRA124_CLK_SATA_COLD 129 153*4882a593Smuzhiyun /* 130 */ 154*4882a593Smuzhiyun /* 131 */ 155*4882a593Smuzhiyun /* 132 */ 156*4882a593Smuzhiyun /* 133 */ 157*4882a593Smuzhiyun /* 134 */ 158*4882a593Smuzhiyun /* 135 */ 159*4882a593Smuzhiyun /* 136 */ 160*4882a593Smuzhiyun /* 137 */ 161*4882a593Smuzhiyun /* 138 */ 162*4882a593Smuzhiyun /* 139 */ 163*4882a593Smuzhiyun /* 140 */ 164*4882a593Smuzhiyun /* 141 */ 165*4882a593Smuzhiyun /* 142 */ 166*4882a593Smuzhiyun /* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ 167*4882a593Smuzhiyun /* xusb_host_src and xusb_ss_src) */ 168*4882a593Smuzhiyun #define TEGRA124_CLK_CILAB 144 169*4882a593Smuzhiyun #define TEGRA124_CLK_CILCD 145 170*4882a593Smuzhiyun #define TEGRA124_CLK_CILE 146 171*4882a593Smuzhiyun #define TEGRA124_CLK_DSIALP 147 172*4882a593Smuzhiyun #define TEGRA124_CLK_DSIBLP 148 173*4882a593Smuzhiyun #define TEGRA124_CLK_ENTROPY 149 174*4882a593Smuzhiyun #define TEGRA124_CLK_DDS 150 175*4882a593Smuzhiyun /* 151 */ 176*4882a593Smuzhiyun #define TEGRA124_CLK_DP2 152 177*4882a593Smuzhiyun #define TEGRA124_CLK_AMX 153 178*4882a593Smuzhiyun #define TEGRA124_CLK_ADX 154 179*4882a593Smuzhiyun /* 155 (bit affects dfll_ref and dfll_soc) */ 180*4882a593Smuzhiyun #define TEGRA124_CLK_XUSB_SS 156 181*4882a593Smuzhiyun /* 157 */ 182*4882a593Smuzhiyun /* 158 */ 183*4882a593Smuzhiyun /* 159 */ 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun /* 160 */ 186*4882a593Smuzhiyun /* 161 */ 187*4882a593Smuzhiyun /* 162 */ 188*4882a593Smuzhiyun /* 163 */ 189*4882a593Smuzhiyun /* 164 */ 190*4882a593Smuzhiyun /* 165 */ 191*4882a593Smuzhiyun #define TEGRA124_CLK_I2C6 166 192*4882a593Smuzhiyun /* 167 */ 193*4882a593Smuzhiyun /* 168 */ 194*4882a593Smuzhiyun /* 169 */ 195*4882a593Smuzhiyun /* 170 */ 196*4882a593Smuzhiyun #define TEGRA124_CLK_VIM2_CLK 171 197*4882a593Smuzhiyun /* 172 */ 198*4882a593Smuzhiyun /* 173 */ 199*4882a593Smuzhiyun /* 174 */ 200*4882a593Smuzhiyun /* 175 */ 201*4882a593Smuzhiyun #define TEGRA124_CLK_HDMI_AUDIO 176 202*4882a593Smuzhiyun #define TEGRA124_CLK_CLK72MHZ 177 203*4882a593Smuzhiyun #define TEGRA124_CLK_VIC03 178 204*4882a593Smuzhiyun /* 179 */ 205*4882a593Smuzhiyun #define TEGRA124_CLK_ADX1 180 206*4882a593Smuzhiyun #define TEGRA124_CLK_DPAUX 181 207*4882a593Smuzhiyun #define TEGRA124_CLK_SOR0 182 208*4882a593Smuzhiyun /* 183 */ 209*4882a593Smuzhiyun #define TEGRA124_CLK_GPU 184 210*4882a593Smuzhiyun #define TEGRA124_CLK_AMX1 185 211*4882a593Smuzhiyun /* 186 */ 212*4882a593Smuzhiyun /* 187 */ 213*4882a593Smuzhiyun /* 188 */ 214*4882a593Smuzhiyun /* 189 */ 215*4882a593Smuzhiyun /* 190 */ 216*4882a593Smuzhiyun /* 191 */ 217*4882a593Smuzhiyun #define TEGRA124_CLK_UARTB 192 218*4882a593Smuzhiyun #define TEGRA124_CLK_VFIR 193 219*4882a593Smuzhiyun #define TEGRA124_CLK_SPDIF_IN 194 220*4882a593Smuzhiyun #define TEGRA124_CLK_SPDIF_OUT 195 221*4882a593Smuzhiyun #define TEGRA124_CLK_VI 196 222*4882a593Smuzhiyun #define TEGRA124_CLK_VI_SENSOR 197 223*4882a593Smuzhiyun #define TEGRA124_CLK_FUSE 198 224*4882a593Smuzhiyun #define TEGRA124_CLK_FUSE_BURN 199 225*4882a593Smuzhiyun #define TEGRA124_CLK_CLK_32K 200 226*4882a593Smuzhiyun #define TEGRA124_CLK_CLK_M 201 227*4882a593Smuzhiyun #define TEGRA124_CLK_CLK_M_DIV2 202 228*4882a593Smuzhiyun #define TEGRA124_CLK_CLK_M_DIV4 203 229*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_REF 204 230*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_C 205 231*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_C_OUT1 206 232*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_C2 207 233*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_C3 208 234*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_M 209 235*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_M_OUT1 210 236*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_P 211 237*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_P_OUT1 212 238*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_P_OUT2 213 239*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_P_OUT3 214 240*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_P_OUT4 215 241*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_A 216 242*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_A_OUT0 217 243*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_D 218 244*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_D_OUT0 219 245*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_D2 220 246*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_D2_OUT0 221 247*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_U 222 248*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_U_480M 223 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_U_60M 224 251*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_U_48M 225 252*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_U_12M 226 253*4882a593Smuzhiyun /* 227 */ 254*4882a593Smuzhiyun /* 228 */ 255*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_RE_VCO 229 256*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_RE_OUT 230 257*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_E 231 258*4882a593Smuzhiyun #define TEGRA124_CLK_SPDIF_IN_SYNC 232 259*4882a593Smuzhiyun #define TEGRA124_CLK_I2S0_SYNC 233 260*4882a593Smuzhiyun #define TEGRA124_CLK_I2S1_SYNC 234 261*4882a593Smuzhiyun #define TEGRA124_CLK_I2S2_SYNC 235 262*4882a593Smuzhiyun #define TEGRA124_CLK_I2S3_SYNC 236 263*4882a593Smuzhiyun #define TEGRA124_CLK_I2S4_SYNC 237 264*4882a593Smuzhiyun #define TEGRA124_CLK_VIMCLK_SYNC 238 265*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO0 239 266*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO1 240 267*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO2 241 268*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO3 242 269*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO4 243 270*4882a593Smuzhiyun #define TEGRA124_CLK_SPDIF 244 271*4882a593Smuzhiyun #define TEGRA124_CLK_CLK_OUT_1 245 272*4882a593Smuzhiyun #define TEGRA124_CLK_CLK_OUT_2 246 273*4882a593Smuzhiyun #define TEGRA124_CLK_CLK_OUT_3 247 274*4882a593Smuzhiyun #define TEGRA124_CLK_BLINK 248 275*4882a593Smuzhiyun /* 249 */ 276*4882a593Smuzhiyun /* 250 */ 277*4882a593Smuzhiyun /* 251 */ 278*4882a593Smuzhiyun #define TEGRA124_CLK_XUSB_HOST_SRC 252 279*4882a593Smuzhiyun #define TEGRA124_CLK_XUSB_FALCON_SRC 253 280*4882a593Smuzhiyun #define TEGRA124_CLK_XUSB_FS_SRC 254 281*4882a593Smuzhiyun #define TEGRA124_CLK_XUSB_SS_SRC 255 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun #define TEGRA124_CLK_XUSB_DEV_SRC 256 284*4882a593Smuzhiyun #define TEGRA124_CLK_XUSB_DEV 257 285*4882a593Smuzhiyun #define TEGRA124_CLK_XUSB_HS_SRC 258 286*4882a593Smuzhiyun #define TEGRA124_CLK_SCLK 259 287*4882a593Smuzhiyun #define TEGRA124_CLK_HCLK 260 288*4882a593Smuzhiyun #define TEGRA124_CLK_PCLK 261 289*4882a593Smuzhiyun /* 262 */ 290*4882a593Smuzhiyun /* 263 */ 291*4882a593Smuzhiyun #define TEGRA124_CLK_DFLL_REF 264 292*4882a593Smuzhiyun #define TEGRA124_CLK_DFLL_SOC 265 293*4882a593Smuzhiyun #define TEGRA124_CLK_VI_SENSOR2 266 294*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_P_OUT5 267 295*4882a593Smuzhiyun #define TEGRA124_CLK_CML0 268 296*4882a593Smuzhiyun #define TEGRA124_CLK_CML1 269 297*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_C4 270 298*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_DP 271 299*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_E_MUX 272 300*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_D_DSI_OUT 273 301*4882a593Smuzhiyun /* 274 */ 302*4882a593Smuzhiyun /* 275 */ 303*4882a593Smuzhiyun /* 276 */ 304*4882a593Smuzhiyun /* 277 */ 305*4882a593Smuzhiyun /* 278 */ 306*4882a593Smuzhiyun /* 279 */ 307*4882a593Smuzhiyun /* 280 */ 308*4882a593Smuzhiyun /* 281 */ 309*4882a593Smuzhiyun /* 282 */ 310*4882a593Smuzhiyun /* 283 */ 311*4882a593Smuzhiyun /* 284 */ 312*4882a593Smuzhiyun /* 285 */ 313*4882a593Smuzhiyun /* 286 */ 314*4882a593Smuzhiyun /* 287 */ 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun /* 288 */ 317*4882a593Smuzhiyun /* 289 */ 318*4882a593Smuzhiyun /* 290 */ 319*4882a593Smuzhiyun /* 291 */ 320*4882a593Smuzhiyun /* 292 */ 321*4882a593Smuzhiyun /* 293 */ 322*4882a593Smuzhiyun /* 294 */ 323*4882a593Smuzhiyun /* 295 */ 324*4882a593Smuzhiyun /* 296 */ 325*4882a593Smuzhiyun /* 297 */ 326*4882a593Smuzhiyun /* 298 */ 327*4882a593Smuzhiyun /* 299 */ 328*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO0_MUX 300 329*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO1_MUX 301 330*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO2_MUX 302 331*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO3_MUX 303 332*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO4_MUX 304 333*4882a593Smuzhiyun #define TEGRA124_CLK_SPDIF_MUX 305 334*4882a593Smuzhiyun #define TEGRA124_CLK_CLK_OUT_1_MUX 306 335*4882a593Smuzhiyun #define TEGRA124_CLK_CLK_OUT_2_MUX 307 336*4882a593Smuzhiyun #define TEGRA124_CLK_CLK_OUT_3_MUX 308 337*4882a593Smuzhiyun /* 309 */ 338*4882a593Smuzhiyun /* 310 */ 339*4882a593Smuzhiyun #define TEGRA124_CLK_SOR0_LVDS 311 340*4882a593Smuzhiyun #define TEGRA124_CLK_XUSB_SS_DIV2 312 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_M_UD 313 343*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_C_UD 314 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */ 346