1 /* 2 * Copyright (c) 2017 Rockchip Electronics Co. Ltd. 3 * Author: Shawn Lin <shawn.lin@rock-chips.com> 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H 9 10 /* pll id */ 11 #define PLL_APLL 0 12 #define PLL_DPLL 1 13 #define PLL_GPLL 2 14 #define ARMCLK 3 15 16 /* sclk gates (special clocks) */ 17 #define SCLK_SPI0 65 18 #define SCLK_NANDC 67 19 #define SCLK_SDMMC 68 20 #define SCLK_SDIO 69 21 #define SCLK_EMMC 71 22 #define SCLK_UART0 72 23 #define SCLK_UART1 73 24 #define SCLK_UART2 74 25 #define SCLK_I2S0 75 26 #define SCLK_I2S1 76 27 #define SCLK_I2S2 77 28 #define SCLK_TIMER0 78 29 #define SCLK_TIMER1 79 30 #define SCLK_SFC 80 31 #define SCLK_SDMMC_DRV 81 32 #define SCLK_SDIO_DRV 82 33 #define SCLK_EMMC_DRV 83 34 #define SCLK_SDMMC_SAMPLE 84 35 #define SCLK_SDIO_SAMPLE 85 36 #define SCLK_EMMC_SAMPLE 86 37 #define SCLK_VENC_CORE 87 38 #define SCLK_HEVC_CORE 88 39 #define SCLK_HEVC_CABAC 89 40 #define SCLK_PWM0_PMU 90 41 #define SCLK_I2C0_PMU 91 42 #define SCLK_WIFI 92 43 #define SCLK_CIFOUT 93 44 #define SCLK_MIPI_CSI_OUT 94 45 #define SCLK_CIF0 95 46 #define SCLK_CIF1 96 47 #define SCLK_CIF2 97 48 #define SCLK_CIF3 98 49 #define SCLK_DSP 99 50 #define SCLK_DSP_IOP 100 51 #define SCLK_DSP_EPP 101 52 #define SCLK_DSP_EDP 102 53 #define SCLK_DSP_EDAP 103 54 #define SCLK_CVBS_HOST 104 55 #define SCLK_HDMI_SFR 105 56 #define SCLK_HDMI_CEC 106 57 #define SCLK_CRYPTO 107 58 #define SCLK_SPI 108 59 #define SCLK_SARADC 109 60 #define SCLK_TSADC 110 61 #define SCLK_MAC_PRE 111 62 #define SCLK_MAC 112 63 #define SCLK_MAC_RX 113 64 #define SCLK_MAC_REF 114 65 #define SCLK_MAC_REFOUT 115 66 #define SCLK_DSP_PFM 116 67 #define SCLK_RGA 117 68 #define SCLK_I2C1 118 69 #define SCLK_I2C2 119 70 #define SCLK_I2C3 120 71 #define SCLK_PWM 121 72 #define SCLK_ISP 122 73 #define SCLK_USBPHY 123 74 #define SCLK_I2S0_SRC 124 75 #define SCLK_I2S1_SRC 125 76 #define SCLK_I2S2_SRC 126 77 #define SCLK_UART0_SRC 127 78 #define SCLK_UART1_SRC 128 79 #define SCLK_UART2_SRC 129 80 #define SCLK_MAC_TX 130 81 82 #define DCLK_VOP_SRC 185 83 #define DCLK_HDMIPHY 186 84 #define DCLK_VOP 187 85 86 /* aclk gates */ 87 #define ACLK_DMAC 192 88 #define ACLK_PRE 193 89 #define ACLK_CORE 194 90 #define ACLK_ENMCORE 195 91 #define ACLK_RKVENC 196 92 #define ACLK_RKVDEC 197 93 #define ACLK_VPU 198 94 #define ACLK_CIF0 199 95 #define ACLK_VIO0 200 96 #define ACLK_VIO1 201 97 #define ACLK_VOP 202 98 #define ACLK_IEP 203 99 #define ACLK_RGA 204 100 #define ACLK_ISP 205 101 #define ACLK_CIF1 206 102 #define ACLK_CIF2 207 103 #define ACLK_CIF3 208 104 #define ACLK_PERI 209 105 #define ACLK_GMAC 210 106 107 /* pclk gates */ 108 #define PCLK_GPIO1 256 109 #define PCLK_GPIO2 257 110 #define PCLK_GPIO3 258 111 #define PCLK_GRF 259 112 #define PCLK_I2C1 260 113 #define PCLK_I2C2 261 114 #define PCLK_I2C3 262 115 #define PCLK_SPI 263 116 #define PCLK_SFC 264 117 #define PCLK_UART0 265 118 #define PCLK_UART1 266 119 #define PCLK_UART2 267 120 #define PCLK_TSADC 268 121 #define PCLK_PWM 269 122 #define PCLK_TIMER 270 123 #define PCLK_PERI 271 124 #define PCLK_GPIO0_PMU 272 125 #define PCLK_I2C0_PMU 273 126 #define PCLK_PWM0_PMU 274 127 #define PCLK_ISP 275 128 #define PCLK_VIO 276 129 #define PCLK_MIPI_DSI 277 130 #define PCLK_HDMI_CTRL 278 131 #define PCLK_SARADC 279 132 #define PCLK_DSP_CFG 280 133 #define PCLK_BUS 281 134 #define PCLK_EFUSE0 282 135 #define PCLK_EFUSE1 283 136 #define PCLK_WDT 284 137 #define PCLK_GMAC 285 138 139 /* hclk gates */ 140 #define HCLK_I2S0_8CH 320 141 #define HCLK_I2S1_2CH 321 142 #define HCLK_I2S2_2CH 322 143 #define HCLK_NANDC 323 144 #define HCLK_SDMMC 324 145 #define HCLK_SDIO 325 146 #define HCLK_EMMC 326 147 #define HCLK_PERI 327 148 #define HCLK_SFC 328 149 #define HCLK_RKVENC 329 150 #define HCLK_RKVDEC 330 151 #define HCLK_CIF0 331 152 #define HCLK_VIO 332 153 #define HCLK_VOP 333 154 #define HCLK_IEP 334 155 #define HCLK_RGA 335 156 #define HCLK_ISP 336 157 #define HCLK_CRYPTO_MST 337 158 #define HCLK_CRYPTO_SLV 338 159 #define HCLK_HOST0 339 160 #define HCLK_OTG 340 161 #define HCLK_CIF1 341 162 #define HCLK_CIF2 342 163 #define HCLK_CIF3 343 164 #define HCLK_BUS 344 165 #define HCLK_VPU 345 166 167 #define CLK_NR_CLKS (HCLK_VPU + 1) 168 169 /* reset id */ 170 #define SRST_CORE_PO_AD 0 171 #define SRST_CORE_AD 1 172 #define SRST_L2_AD 2 173 #define SRST_CPU_NIU_AD 3 174 #define SRST_CORE_PO 4 175 #define SRST_CORE 5 176 #define SRST_L2 6 177 #define SRST_CORE_DBG 8 178 #define PRST_DBG 9 179 #define RST_DAP 10 180 #define PRST_DBG_NIU 11 181 #define ARST_STRC_SYS_AD 15 182 183 #define SRST_DDRPHY_CLKDIV 16 184 #define SRST_DDRPHY 17 185 #define PRST_DDRPHY 18 186 #define PRST_HDMIPHY 19 187 #define PRST_VDACPHY 20 188 #define PRST_VADCPHY 21 189 #define PRST_MIPI_CSI_PHY 22 190 #define PRST_MIPI_DSI_PHY 23 191 #define PRST_ACODEC 24 192 #define ARST_BUS_NIU 25 193 #define PRST_TOP_NIU 26 194 #define ARST_INTMEM 27 195 #define HRST_ROM 28 196 #define ARST_DMAC 29 197 #define SRST_MSCH_NIU 30 198 #define PRST_MSCH_NIU 31 199 200 #define PRST_DDRUPCTL 32 201 #define NRST_DDRUPCTL 33 202 #define PRST_DDRMON 34 203 #define HRST_I2S0_8CH 35 204 #define MRST_I2S0_8CH 36 205 #define HRST_I2S1_2CH 37 206 #define MRST_IS21_2CH 38 207 #define HRST_I2S2_2CH 39 208 #define MRST_I2S2_2CH 40 209 #define HRST_CRYPTO 41 210 #define SRST_CRYPTO 42 211 #define PRST_SPI 43 212 #define SRST_SPI 44 213 #define PRST_UART0 45 214 #define PRST_UART1 46 215 #define PRST_UART2 47 216 217 #define SRST_UART0 48 218 #define SRST_UART1 49 219 #define SRST_UART2 50 220 #define PRST_I2C1 51 221 #define PRST_I2C2 52 222 #define PRST_I2C3 53 223 #define SRST_I2C1 54 224 #define SRST_I2C2 55 225 #define SRST_I2C3 56 226 #define PRST_PWM1 58 227 #define SRST_PWM1 60 228 #define PRST_WDT 61 229 #define PRST_GPIO1 62 230 #define PRST_GPIO2 63 231 232 #define PRST_GPIO3 64 233 #define PRST_GRF 65 234 #define PRST_EFUSE 66 235 #define PRST_EFUSE512 67 236 #define PRST_TIMER0 68 237 #define SRST_TIMER0 69 238 #define SRST_TIMER1 70 239 #define PRST_TSADC 71 240 #define SRST_TSADC 72 241 #define PRST_SARADC 73 242 #define SRST_SARADC 74 243 #define HRST_SYSBUS 75 244 #define PRST_USBGRF 76 245 246 #define ARST_PERIPH_NIU 80 247 #define HRST_PERIPH_NIU 81 248 #define PRST_PERIPH_NIU 82 249 #define HRST_PERIPH 83 250 #define HRST_SDMMC 84 251 #define HRST_SDIO 85 252 #define HRST_EMMC 86 253 #define HRST_NANDC 87 254 #define NRST_NANDC 88 255 #define HRST_SFC 89 256 #define SRST_SFC 90 257 #define ARST_GMAC 91 258 #define HRST_OTG 92 259 #define SRST_OTG 93 260 #define SRST_OTG_ADP 94 261 #define HRST_HOST0 95 262 263 #define HRST_HOST0_AUX 96 264 #define HRST_HOST0_ARB 97 265 #define SRST_HOST0_EHCIPHY 98 266 #define SRST_HOST0_UTMI 99 267 #define SRST_USBPOR 100 268 #define SRST_UTMI0 101 269 #define SRST_UTMI1 102 270 271 #define ARST_VIO0_NIU 102 272 #define ARST_VIO1_NIU 103 273 #define HRST_VIO_NIU 104 274 #define PRST_VIO_NIU 105 275 #define ARST_VOP 106 276 #define HRST_VOP 107 277 #define DRST_VOP 108 278 #define ARST_IEP 109 279 #define HRST_IEP 110 280 #define ARST_RGA 111 281 #define HRST_RGA 112 282 #define SRST_RGA 113 283 #define PRST_CVBS 114 284 #define PRST_HDMI 115 285 #define SRST_HDMI 116 286 #define PRST_MIPI_DSI 117 287 288 #define ARST_ISP_NIU 118 289 #define HRST_ISP_NIU 119 290 #define HRST_ISP 120 291 #define SRST_ISP 121 292 #define ARST_VIP0 122 293 #define HRST_VIP0 123 294 #define PRST_VIP0 124 295 #define ARST_VIP1 125 296 #define HRST_VIP1 126 297 #define PRST_VIP1 127 298 #define ARST_VIP2 128 299 #define HRST_VIP2 129 300 #define PRST_VIP2 120 301 #define ARST_VIP3 121 302 #define HRST_VIP3 122 303 #define PRST_VIP4 123 304 305 #define PRST_CIF1TO4 124 306 #define SRST_CVBS_CLK 125 307 #define HRST_CVBS 126 308 309 #define ARST_VPU_NIU 140 310 #define HRST_VPU_NIU 141 311 #define ARST_VPU 142 312 #define HRST_VPU 143 313 #define ARST_RKVDEC_NIU 144 314 #define HRST_RKVDEC_NIU 145 315 #define ARST_RKVDEC 146 316 #define HRST_RKVDEC 147 317 #define SRST_RKVDEC_CABAC 148 318 #define SRST_RKVDEC_CORE 149 319 #define ARST_RKVENC_NIU 150 320 #define HRST_RKVENC_NIU 151 321 #define ARST_RKVENC 152 322 #define HRST_RKVENC 153 323 #define SRST_RKVENC_CORE 154 324 325 #define SRST_DSP_CORE 156 326 #define SRST_DSP_SYS 157 327 #define SRST_DSP_GLOBAL 158 328 #define SRST_DSP_OECM 159 329 #define PRST_DSP_IOP_NIU 160 330 #define ARST_DSP_EPP_NIU 161 331 #define ARST_DSP_EDP_NIU 162 332 #define PRST_DSP_DBG_NIU 163 333 #define PRST_DSP_CFG_NIU 164 334 #define PRST_DSP_GRF 165 335 #define PRST_DSP_MAILBOX 166 336 #define PRST_DSP_INTC 167 337 #define PRST_DSP_PFM_MON 169 338 #define SRST_DSP_PFM_MON 170 339 #define ARST_DSP_EDAP_NIU 171 340 341 #define SRST_PMU 172 342 #define SRST_PMU_I2C0 173 343 #define PRST_PMU_I2C0 174 344 #define PRST_PMU_GPIO0 175 345 #define PRST_PMU_INTMEM 176 346 #define PRST_PMU_PWM0 177 347 #define SRST_PMU_PWM0 178 348 #define PRST_PMU_GRF 179 349 #define SRST_PMU_NIU 180 350 #define SRST_PMU_PVTM 181 351 #define ARST_DSP_EDP_PERF 184 352 #define ARST_DSP_EPP_PERF 185 353 354 #endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */ 355