1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __CLK_MICROCHIP_PIC32 9*4882a593Smuzhiyun #define __CLK_MICROCHIP_PIC32 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* clock output indices */ 12*4882a593Smuzhiyun #define BASECLK 0 13*4882a593Smuzhiyun #define PLLCLK 1 14*4882a593Smuzhiyun #define MPLL 2 15*4882a593Smuzhiyun #define SYSCLK 3 16*4882a593Smuzhiyun #define PB1CLK 4 17*4882a593Smuzhiyun #define PB2CLK 5 18*4882a593Smuzhiyun #define PB3CLK 6 19*4882a593Smuzhiyun #define PB4CLK 7 20*4882a593Smuzhiyun #define PB5CLK 8 21*4882a593Smuzhiyun #define PB6CLK 9 22*4882a593Smuzhiyun #define PB7CLK 10 23*4882a593Smuzhiyun #define REF1CLK 11 24*4882a593Smuzhiyun #define REF2CLK 12 25*4882a593Smuzhiyun #define REF3CLK 13 26*4882a593Smuzhiyun #define REF4CLK 14 27*4882a593Smuzhiyun #define REF5CLK 15 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #endif /* __CLK_MICROCHIP_PIC32 */ 30