1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2016 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 5*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 6*4882a593Smuzhiyun * published by the Free Software Foundation. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H 11*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_IMX7ULP_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define IMX7ULP_CLK_DUMMY 0 14*4882a593Smuzhiyun #define IMX7ULP_CLK_CKIL 1 15*4882a593Smuzhiyun #define IMX7ULP_CLK_OSC 2 16*4882a593Smuzhiyun #define IMX7ULP_CLK_FIRC 3 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* SCG1 */ 19*4882a593Smuzhiyun #define IMX7ULP_CLK_SPLL_PRE_SEL 4 20*4882a593Smuzhiyun #define IMX7ULP_CLK_SPLL_PRE_DIV 5 21*4882a593Smuzhiyun #define IMX7ULP_CLK_SPLL 6 22*4882a593Smuzhiyun #define IMX7ULP_CLK_SPLL_POST_DIV1 7 23*4882a593Smuzhiyun #define IMX7ULP_CLK_SPLL_POST_DIV2 8 24*4882a593Smuzhiyun #define IMX7ULP_CLK_SPLL_PFD0 9 25*4882a593Smuzhiyun #define IMX7ULP_CLK_SPLL_PFD1 10 26*4882a593Smuzhiyun #define IMX7ULP_CLK_SPLL_PFD2 11 27*4882a593Smuzhiyun #define IMX7ULP_CLK_SPLL_PFD3 12 28*4882a593Smuzhiyun #define IMX7ULP_CLK_SPLL_PFD_SEL 13 29*4882a593Smuzhiyun #define IMX7ULP_CLK_SPLL_SEL 14 30*4882a593Smuzhiyun #define IMX7ULP_CLK_APLL_PRE_SEL 15 31*4882a593Smuzhiyun #define IMX7ULP_CLK_APLL_PRE_DIV 16 32*4882a593Smuzhiyun #define IMX7ULP_CLK_APLL 17 33*4882a593Smuzhiyun #define IMX7ULP_CLK_APLL_POST_DIV1 18 34*4882a593Smuzhiyun #define IMX7ULP_CLK_APLL_POST_DIV2 19 35*4882a593Smuzhiyun #define IMX7ULP_CLK_APLL_PFD0 20 36*4882a593Smuzhiyun #define IMX7ULP_CLK_APLL_PFD1 21 37*4882a593Smuzhiyun #define IMX7ULP_CLK_APLL_PFD2 22 38*4882a593Smuzhiyun #define IMX7ULP_CLK_APLL_PFD3 23 39*4882a593Smuzhiyun #define IMX7ULP_CLK_APLL_PFD_SEL 24 40*4882a593Smuzhiyun #define IMX7ULP_CLK_APLL_SEL 25 41*4882a593Smuzhiyun #define IMX7ULP_CLK_UPLL 26 42*4882a593Smuzhiyun #define IMX7ULP_CLK_SYS_SEL 27 43*4882a593Smuzhiyun #define IMX7ULP_CLK_CORE_DIV 28 44*4882a593Smuzhiyun #define IMX7ULP_CLK_BUS_DIV 29 45*4882a593Smuzhiyun #define IMX7ULP_CLK_PLAT_DIV 30 46*4882a593Smuzhiyun #define IMX7ULP_CLK_DDR_SEL 31 47*4882a593Smuzhiyun #define IMX7ULP_CLK_DDR_DIV 32 48*4882a593Smuzhiyun #define IMX7ULP_CLK_NIC_SEL 33 49*4882a593Smuzhiyun #define IMX7ULP_CLK_NIC0_DIV 34 50*4882a593Smuzhiyun #define IMX7ULP_CLK_GPU_DIV 35 51*4882a593Smuzhiyun #define IMX7ULP_CLK_NIC1_DIV 36 52*4882a593Smuzhiyun #define IMX7ULP_CLK_NIC1_BUS_DIV 37 53*4882a593Smuzhiyun #define IMX7ULP_CLK_NIC1_EXT_DIV 38 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* PCG2 */ 56*4882a593Smuzhiyun #define IMX7ULP_CLK_DMA1 39 57*4882a593Smuzhiyun #define IMX7ULP_CLK_RGPIO2P1 40 58*4882a593Smuzhiyun #define IMX7ULP_CLK_FLEXBUS 41 59*4882a593Smuzhiyun #define IMX7ULP_CLK_SEMA42_1 42 60*4882a593Smuzhiyun #define IMX7ULP_CLK_DMA_MUX1 43 61*4882a593Smuzhiyun #define IMX7ULP_CLK_SNVS 44 62*4882a593Smuzhiyun #define IMX7ULP_CLK_CAAM 45 63*4882a593Smuzhiyun #define IMX7ULP_CLK_LPTPM4 46 64*4882a593Smuzhiyun #define IMX7ULP_CLK_LPTPM5 47 65*4882a593Smuzhiyun #define IMX7ULP_CLK_LPIT1 48 66*4882a593Smuzhiyun #define IMX7ULP_CLK_LPSPI2 49 67*4882a593Smuzhiyun #define IMX7ULP_CLK_LPSPI3 50 68*4882a593Smuzhiyun #define IMX7ULP_CLK_LPI2C4 51 69*4882a593Smuzhiyun #define IMX7ULP_CLK_LPI2C5 52 70*4882a593Smuzhiyun #define IMX7ULP_CLK_LPUART4 53 71*4882a593Smuzhiyun #define IMX7ULP_CLK_LPUART5 54 72*4882a593Smuzhiyun #define IMX7ULP_CLK_FLEXIO1 55 73*4882a593Smuzhiyun #define IMX7ULP_CLK_USB0 56 74*4882a593Smuzhiyun #define IMX7ULP_CLK_USB1 57 75*4882a593Smuzhiyun #define IMX7ULP_CLK_USB_PHY 58 76*4882a593Smuzhiyun #define IMX7ULP_CLK_USB_PL301 59 77*4882a593Smuzhiyun #define IMX7ULP_CLK_USDHC0 60 78*4882a593Smuzhiyun #define IMX7ULP_CLK_USDHC1 61 79*4882a593Smuzhiyun #define IMX7ULP_CLK_WDG1 62 80*4882a593Smuzhiyun #define IMX7ULP_CLK_WDG2 63 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* PCG3 */ 83*4882a593Smuzhiyun #define IMX7ULP_CLK_LPTPM6 64 84*4882a593Smuzhiyun #define IMX7ULP_CLK_LPTPM7 65 85*4882a593Smuzhiyun #define IMX7ULP_CLK_LPI2C6 66 86*4882a593Smuzhiyun #define IMX7ULP_CLK_LPI2C7 67 87*4882a593Smuzhiyun #define IMX7ULP_CLK_LPUART6 68 88*4882a593Smuzhiyun #define IMX7ULP_CLK_LPUART7 69 89*4882a593Smuzhiyun #define IMX7ULP_CLK_VIU 70 90*4882a593Smuzhiyun #define IMX7ULP_CLK_DSI 71 91*4882a593Smuzhiyun #define IMX7ULP_CLK_LCDIF 72 92*4882a593Smuzhiyun #define IMX7ULP_CLK_MMDC 73 93*4882a593Smuzhiyun #define IMX7ULP_CLK_PCTLC 74 94*4882a593Smuzhiyun #define IMX7ULP_CLK_PCTLD 75 95*4882a593Smuzhiyun #define IMX7ULP_CLK_PCTLE 76 96*4882a593Smuzhiyun #define IMX7ULP_CLK_PCTLF 77 97*4882a593Smuzhiyun #define IMX7ULP_CLK_GPU3D 78 98*4882a593Smuzhiyun #define IMX7ULP_CLK_GPU2D 79 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define IMX7ULP_CLK_MIPI_PLL 80 101*4882a593Smuzhiyun #define IMX7ULP_CLK_SIRC 81 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define IMX7ULP_CLK_SCG1_CLKOUT 82 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define IMX7ULP_CLK_END 83 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /*cm4 clocks*/ 108*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_DUMMY 0 109*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_CKIL 1 110*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_OSC 2 111*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_FIRC 3 112*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SIRC 4 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* SCG0 */ 115*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_SEL 5 116*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_DIV 6 117*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SPLL 7 118*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SPLL_VCO 8 119*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV1 9 120*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV2 10 121*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SPLL_PFD0 11 122*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SPLL_PFD1 12 123*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SPLL_PFD2 13 124*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SPLL_PFD3 14 125*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SPLL_PFD_SEL 15 126*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SPLL_PFD 16 127*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SPLL_SEL 17 128*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_APLL_VCO_PRE_SEL 18 129*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_APLL_VCO_PRE_DIV 19 130*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_APLL 20 131*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_APLL_VCO 21 132*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV1 22 133*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV2 23 134*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_APLL_PFD0 24 135*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_APLL_PFD1 25 136*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_APLL_PFD2 26 137*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_APLL_PFD3 27 138*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_APLL_PFD_SEL 28 139*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_APLL_PFD 29 140*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_APLL_SEL 30 141*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_APLL_PFD0_PRE_DIV 31 142*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SYS_SEL 32 143*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_CORE_DIV 33 144*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_BUS_DIV 34 145*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_PLAT_DIV 35 146*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SLOW_DIV 36 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SAI0_SEL 37 149*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SAI0_DIV 38 150*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SAI0_ROOT 39 151*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SAI0_IPG 40 152*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SAI1_SEL 41 153*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SAI1_DIV 42 154*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SAI1_ROOT 43 155*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_SAI1_IPG 44 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #define IMX7ULP_CLK_SCG0_CLKOUT 45 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #define IMX7ULP_CM4_CLK_END 46 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */ 162