1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 5*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 6*4882a593Smuzhiyun * published by the Free Software Foundation. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_IMX7D_H 11*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_IMX7D_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define IMX7D_OSC_24M_CLK 0 14*4882a593Smuzhiyun #define IMX7D_PLL_ARM_MAIN 1 15*4882a593Smuzhiyun #define IMX7D_PLL_ARM_MAIN_CLK 2 16*4882a593Smuzhiyun #define IMX7D_PLL_ARM_MAIN_SRC 3 17*4882a593Smuzhiyun #define IMX7D_PLL_ARM_MAIN_BYPASS 4 18*4882a593Smuzhiyun #define IMX7D_PLL_SYS_MAIN 5 19*4882a593Smuzhiyun #define IMX7D_PLL_SYS_MAIN_CLK 6 20*4882a593Smuzhiyun #define IMX7D_PLL_SYS_MAIN_SRC 7 21*4882a593Smuzhiyun #define IMX7D_PLL_SYS_MAIN_BYPASS 8 22*4882a593Smuzhiyun #define IMX7D_PLL_SYS_MAIN_480M 9 23*4882a593Smuzhiyun #define IMX7D_PLL_SYS_MAIN_240M 10 24*4882a593Smuzhiyun #define IMX7D_PLL_SYS_MAIN_120M 11 25*4882a593Smuzhiyun #define IMX7D_PLL_SYS_MAIN_480M_CLK 12 26*4882a593Smuzhiyun #define IMX7D_PLL_SYS_MAIN_240M_CLK 13 27*4882a593Smuzhiyun #define IMX7D_PLL_SYS_MAIN_120M_CLK 14 28*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD0_392M_CLK 15 29*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD0_196M 16 30*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD0_196M_CLK 17 31*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD1_332M_CLK 18 32*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD1_166M 19 33*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD1_166M_CLK 20 34*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD2_270M_CLK 21 35*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD2_135M 22 36*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD2_135M_CLK 23 37*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD3_CLK 24 38*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD4_CLK 25 39*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD5_CLK 26 40*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD6_CLK 27 41*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD7_CLK 28 42*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN 29 43*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_CLK 30 44*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_SRC 31 45*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_BYPASS 32 46*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_500M 33 47*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_250M 34 48*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_125M 35 49*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_100M 36 50*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_50M 37 51*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_40M 38 52*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_25M 39 53*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_500M_CLK 40 54*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_250M_CLK 41 55*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_125M_CLK 42 56*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_100M_CLK 43 57*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_50M_CLK 44 58*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_40M_CLK 45 59*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_25M_CLK 46 60*4882a593Smuzhiyun #define IMX7D_PLL_DRAM_MAIN 47 61*4882a593Smuzhiyun #define IMX7D_PLL_DRAM_MAIN_CLK 48 62*4882a593Smuzhiyun #define IMX7D_PLL_DRAM_MAIN_SRC 49 63*4882a593Smuzhiyun #define IMX7D_PLL_DRAM_MAIN_BYPASS 50 64*4882a593Smuzhiyun #define IMX7D_PLL_DRAM_MAIN_533M 51 65*4882a593Smuzhiyun #define IMX7D_PLL_DRAM_MAIN_533M_CLK 52 66*4882a593Smuzhiyun #define IMX7D_PLL_AUDIO_MAIN 53 67*4882a593Smuzhiyun #define IMX7D_PLL_AUDIO_MAIN_CLK 54 68*4882a593Smuzhiyun #define IMX7D_PLL_AUDIO_MAIN_SRC 55 69*4882a593Smuzhiyun #define IMX7D_PLL_AUDIO_MAIN_BYPASS 56 70*4882a593Smuzhiyun #define IMX7D_PLL_VIDEO_MAIN_CLK 57 71*4882a593Smuzhiyun #define IMX7D_PLL_VIDEO_MAIN 58 72*4882a593Smuzhiyun #define IMX7D_PLL_VIDEO_MAIN_SRC 59 73*4882a593Smuzhiyun #define IMX7D_PLL_VIDEO_MAIN_BYPASS 60 74*4882a593Smuzhiyun #define IMX7D_USB_MAIN_480M_CLK 61 75*4882a593Smuzhiyun #define IMX7D_ARM_A7_ROOT_CLK 62 76*4882a593Smuzhiyun #define IMX7D_ARM_A7_ROOT_SRC 63 77*4882a593Smuzhiyun #define IMX7D_ARM_A7_ROOT_CG 64 78*4882a593Smuzhiyun #define IMX7D_ARM_A7_ROOT_DIV 65 79*4882a593Smuzhiyun #define IMX7D_ARM_M4_ROOT_CLK 66 80*4882a593Smuzhiyun #define IMX7D_ARM_M4_ROOT_SRC 67 81*4882a593Smuzhiyun #define IMX7D_ARM_M4_ROOT_CG 68 82*4882a593Smuzhiyun #define IMX7D_ARM_M4_ROOT_DIV 69 83*4882a593Smuzhiyun #define IMX7D_ARM_M0_ROOT_CLK 70 84*4882a593Smuzhiyun #define IMX7D_ARM_M0_ROOT_SRC 71 85*4882a593Smuzhiyun #define IMX7D_ARM_M0_ROOT_CG 72 86*4882a593Smuzhiyun #define IMX7D_ARM_M0_ROOT_DIV 73 87*4882a593Smuzhiyun #define IMX7D_MAIN_AXI_ROOT_CLK 74 88*4882a593Smuzhiyun #define IMX7D_MAIN_AXI_ROOT_SRC 75 89*4882a593Smuzhiyun #define IMX7D_MAIN_AXI_ROOT_CG 76 90*4882a593Smuzhiyun #define IMX7D_MAIN_AXI_ROOT_DIV 77 91*4882a593Smuzhiyun #define IMX7D_DISP_AXI_ROOT_CLK 78 92*4882a593Smuzhiyun #define IMX7D_DISP_AXI_ROOT_SRC 79 93*4882a593Smuzhiyun #define IMX7D_DISP_AXI_ROOT_CG 80 94*4882a593Smuzhiyun #define IMX7D_DISP_AXI_ROOT_DIV 81 95*4882a593Smuzhiyun #define IMX7D_ENET_AXI_ROOT_CLK 82 96*4882a593Smuzhiyun #define IMX7D_ENET_AXI_ROOT_SRC 83 97*4882a593Smuzhiyun #define IMX7D_ENET_AXI_ROOT_CG 84 98*4882a593Smuzhiyun #define IMX7D_ENET_AXI_ROOT_DIV 85 99*4882a593Smuzhiyun #define IMX7D_NAND_USDHC_BUS_ROOT_CLK 86 100*4882a593Smuzhiyun #define IMX7D_NAND_USDHC_BUS_ROOT_SRC 87 101*4882a593Smuzhiyun #define IMX7D_NAND_USDHC_BUS_ROOT_CG 88 102*4882a593Smuzhiyun #define IMX7D_NAND_USDHC_BUS_ROOT_DIV 89 103*4882a593Smuzhiyun #define IMX7D_AHB_CHANNEL_ROOT_CLK 90 104*4882a593Smuzhiyun #define IMX7D_AHB_CHANNEL_ROOT_SRC 91 105*4882a593Smuzhiyun #define IMX7D_AHB_CHANNEL_ROOT_CG 92 106*4882a593Smuzhiyun #define IMX7D_AHB_CHANNEL_ROOT_DIV 93 107*4882a593Smuzhiyun #define IMX7D_DRAM_PHYM_ROOT_CLK 94 108*4882a593Smuzhiyun #define IMX7D_DRAM_PHYM_ROOT_SRC 95 109*4882a593Smuzhiyun #define IMX7D_DRAM_PHYM_ROOT_CG 96 110*4882a593Smuzhiyun #define IMX7D_DRAM_PHYM_ROOT_DIV 97 111*4882a593Smuzhiyun #define IMX7D_DRAM_ROOT_CLK 98 112*4882a593Smuzhiyun #define IMX7D_DRAM_ROOT_SRC 99 113*4882a593Smuzhiyun #define IMX7D_DRAM_ROOT_CG 100 114*4882a593Smuzhiyun #define IMX7D_DRAM_ROOT_DIV 101 115*4882a593Smuzhiyun #define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 102 116*4882a593Smuzhiyun #define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 103 117*4882a593Smuzhiyun #define IMX7D_DRAM_PHYM_ALT_ROOT_CG 104 118*4882a593Smuzhiyun #define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 105 119*4882a593Smuzhiyun #define IMX7D_DRAM_ALT_ROOT_CLK 106 120*4882a593Smuzhiyun #define IMX7D_DRAM_ALT_ROOT_SRC 107 121*4882a593Smuzhiyun #define IMX7D_DRAM_ALT_ROOT_CG 108 122*4882a593Smuzhiyun #define IMX7D_DRAM_ALT_ROOT_DIV 109 123*4882a593Smuzhiyun #define IMX7D_USB_HSIC_ROOT_CLK 110 124*4882a593Smuzhiyun #define IMX7D_USB_HSIC_ROOT_SRC 111 125*4882a593Smuzhiyun #define IMX7D_USB_HSIC_ROOT_CG 112 126*4882a593Smuzhiyun #define IMX7D_USB_HSIC_ROOT_DIV 113 127*4882a593Smuzhiyun #define IMX7D_PCIE_CTRL_ROOT_CLK 114 128*4882a593Smuzhiyun #define IMX7D_PCIE_CTRL_ROOT_SRC 115 129*4882a593Smuzhiyun #define IMX7D_PCIE_CTRL_ROOT_CG 116 130*4882a593Smuzhiyun #define IMX7D_PCIE_CTRL_ROOT_DIV 117 131*4882a593Smuzhiyun #define IMX7D_PCIE_PHY_ROOT_CLK 118 132*4882a593Smuzhiyun #define IMX7D_PCIE_PHY_ROOT_SRC 119 133*4882a593Smuzhiyun #define IMX7D_PCIE_PHY_ROOT_CG 120 134*4882a593Smuzhiyun #define IMX7D_PCIE_PHY_ROOT_DIV 121 135*4882a593Smuzhiyun #define IMX7D_EPDC_PIXEL_ROOT_CLK 122 136*4882a593Smuzhiyun #define IMX7D_EPDC_PIXEL_ROOT_SRC 123 137*4882a593Smuzhiyun #define IMX7D_EPDC_PIXEL_ROOT_CG 124 138*4882a593Smuzhiyun #define IMX7D_EPDC_PIXEL_ROOT_DIV 125 139*4882a593Smuzhiyun #define IMX7D_LCDIF_PIXEL_ROOT_CLK 126 140*4882a593Smuzhiyun #define IMX7D_LCDIF_PIXEL_ROOT_SRC 127 141*4882a593Smuzhiyun #define IMX7D_LCDIF_PIXEL_ROOT_CG 128 142*4882a593Smuzhiyun #define IMX7D_LCDIF_PIXEL_ROOT_DIV 129 143*4882a593Smuzhiyun #define IMX7D_MIPI_DSI_ROOT_CLK 130 144*4882a593Smuzhiyun #define IMX7D_MIPI_DSI_ROOT_SRC 131 145*4882a593Smuzhiyun #define IMX7D_MIPI_DSI_ROOT_CG 132 146*4882a593Smuzhiyun #define IMX7D_MIPI_DSI_ROOT_DIV 133 147*4882a593Smuzhiyun #define IMX7D_MIPI_CSI_ROOT_CLK 134 148*4882a593Smuzhiyun #define IMX7D_MIPI_CSI_ROOT_SRC 135 149*4882a593Smuzhiyun #define IMX7D_MIPI_CSI_ROOT_CG 136 150*4882a593Smuzhiyun #define IMX7D_MIPI_CSI_ROOT_DIV 137 151*4882a593Smuzhiyun #define IMX7D_MIPI_DPHY_ROOT_CLK 138 152*4882a593Smuzhiyun #define IMX7D_MIPI_DPHY_ROOT_SRC 139 153*4882a593Smuzhiyun #define IMX7D_MIPI_DPHY_ROOT_CG 140 154*4882a593Smuzhiyun #define IMX7D_MIPI_DPHY_ROOT_DIV 141 155*4882a593Smuzhiyun #define IMX7D_SAI1_ROOT_CLK 142 156*4882a593Smuzhiyun #define IMX7D_SAI1_ROOT_SRC 143 157*4882a593Smuzhiyun #define IMX7D_SAI1_ROOT_CG 144 158*4882a593Smuzhiyun #define IMX7D_SAI1_ROOT_DIV 145 159*4882a593Smuzhiyun #define IMX7D_SAI2_ROOT_CLK 146 160*4882a593Smuzhiyun #define IMX7D_SAI2_ROOT_SRC 147 161*4882a593Smuzhiyun #define IMX7D_SAI2_ROOT_CG 148 162*4882a593Smuzhiyun #define IMX7D_SAI2_ROOT_DIV 149 163*4882a593Smuzhiyun #define IMX7D_SAI3_ROOT_CLK 150 164*4882a593Smuzhiyun #define IMX7D_SAI3_ROOT_SRC 151 165*4882a593Smuzhiyun #define IMX7D_SAI3_ROOT_CG 152 166*4882a593Smuzhiyun #define IMX7D_SAI3_ROOT_DIV 153 167*4882a593Smuzhiyun #define IMX7D_SPDIF_ROOT_CLK 154 168*4882a593Smuzhiyun #define IMX7D_SPDIF_ROOT_SRC 155 169*4882a593Smuzhiyun #define IMX7D_SPDIF_ROOT_CG 156 170*4882a593Smuzhiyun #define IMX7D_SPDIF_ROOT_DIV 157 171*4882a593Smuzhiyun #define IMX7D_ENET1_REF_ROOT_CLK 158 172*4882a593Smuzhiyun #define IMX7D_ENET1_REF_ROOT_SRC 159 173*4882a593Smuzhiyun #define IMX7D_ENET1_REF_ROOT_CG 160 174*4882a593Smuzhiyun #define IMX7D_ENET1_REF_ROOT_DIV 161 175*4882a593Smuzhiyun #define IMX7D_ENET1_TIME_ROOT_CLK 162 176*4882a593Smuzhiyun #define IMX7D_ENET1_TIME_ROOT_SRC 163 177*4882a593Smuzhiyun #define IMX7D_ENET1_TIME_ROOT_CG 164 178*4882a593Smuzhiyun #define IMX7D_ENET1_TIME_ROOT_DIV 165 179*4882a593Smuzhiyun #define IMX7D_ENET2_REF_ROOT_CLK 166 180*4882a593Smuzhiyun #define IMX7D_ENET2_REF_ROOT_SRC 167 181*4882a593Smuzhiyun #define IMX7D_ENET2_REF_ROOT_CG 168 182*4882a593Smuzhiyun #define IMX7D_ENET2_REF_ROOT_DIV 169 183*4882a593Smuzhiyun #define IMX7D_ENET2_TIME_ROOT_CLK 170 184*4882a593Smuzhiyun #define IMX7D_ENET2_TIME_ROOT_SRC 171 185*4882a593Smuzhiyun #define IMX7D_ENET2_TIME_ROOT_CG 172 186*4882a593Smuzhiyun #define IMX7D_ENET2_TIME_ROOT_DIV 173 187*4882a593Smuzhiyun #define IMX7D_ENET_PHY_REF_ROOT_CLK 174 188*4882a593Smuzhiyun #define IMX7D_ENET_PHY_REF_ROOT_SRC 175 189*4882a593Smuzhiyun #define IMX7D_ENET_PHY_REF_ROOT_CG 176 190*4882a593Smuzhiyun #define IMX7D_ENET_PHY_REF_ROOT_DIV 177 191*4882a593Smuzhiyun #define IMX7D_EIM_ROOT_CLK 178 192*4882a593Smuzhiyun #define IMX7D_EIM_ROOT_SRC 179 193*4882a593Smuzhiyun #define IMX7D_EIM_ROOT_CG 180 194*4882a593Smuzhiyun #define IMX7D_EIM_ROOT_DIV 181 195*4882a593Smuzhiyun #define IMX7D_NAND_ROOT_CLK 182 196*4882a593Smuzhiyun #define IMX7D_NAND_ROOT_SRC 183 197*4882a593Smuzhiyun #define IMX7D_NAND_ROOT_CG 184 198*4882a593Smuzhiyun #define IMX7D_NAND_ROOT_DIV 185 199*4882a593Smuzhiyun #define IMX7D_QSPI_ROOT_CLK 186 200*4882a593Smuzhiyun #define IMX7D_QSPI_ROOT_SRC 187 201*4882a593Smuzhiyun #define IMX7D_QSPI_ROOT_CG 188 202*4882a593Smuzhiyun #define IMX7D_QSPI_ROOT_DIV 189 203*4882a593Smuzhiyun #define IMX7D_USDHC1_ROOT_CLK 190 204*4882a593Smuzhiyun #define IMX7D_USDHC1_ROOT_SRC 191 205*4882a593Smuzhiyun #define IMX7D_USDHC1_ROOT_CG 192 206*4882a593Smuzhiyun #define IMX7D_USDHC1_ROOT_DIV 193 207*4882a593Smuzhiyun #define IMX7D_USDHC2_ROOT_CLK 194 208*4882a593Smuzhiyun #define IMX7D_USDHC2_ROOT_SRC 195 209*4882a593Smuzhiyun #define IMX7D_USDHC2_ROOT_CG 196 210*4882a593Smuzhiyun #define IMX7D_USDHC2_ROOT_DIV 197 211*4882a593Smuzhiyun #define IMX7D_USDHC3_ROOT_CLK 198 212*4882a593Smuzhiyun #define IMX7D_USDHC3_ROOT_SRC 199 213*4882a593Smuzhiyun #define IMX7D_USDHC3_ROOT_CG 200 214*4882a593Smuzhiyun #define IMX7D_USDHC3_ROOT_DIV 201 215*4882a593Smuzhiyun #define IMX7D_CAN1_ROOT_CLK 202 216*4882a593Smuzhiyun #define IMX7D_CAN1_ROOT_SRC 203 217*4882a593Smuzhiyun #define IMX7D_CAN1_ROOT_CG 204 218*4882a593Smuzhiyun #define IMX7D_CAN1_ROOT_DIV 205 219*4882a593Smuzhiyun #define IMX7D_CAN2_ROOT_CLK 206 220*4882a593Smuzhiyun #define IMX7D_CAN2_ROOT_SRC 207 221*4882a593Smuzhiyun #define IMX7D_CAN2_ROOT_CG 208 222*4882a593Smuzhiyun #define IMX7D_CAN2_ROOT_DIV 209 223*4882a593Smuzhiyun #define IMX7D_I2C1_ROOT_CLK 210 224*4882a593Smuzhiyun #define IMX7D_I2C1_ROOT_SRC 211 225*4882a593Smuzhiyun #define IMX7D_I2C1_ROOT_CG 212 226*4882a593Smuzhiyun #define IMX7D_I2C1_ROOT_DIV 213 227*4882a593Smuzhiyun #define IMX7D_I2C2_ROOT_CLK 214 228*4882a593Smuzhiyun #define IMX7D_I2C2_ROOT_SRC 215 229*4882a593Smuzhiyun #define IMX7D_I2C2_ROOT_CG 216 230*4882a593Smuzhiyun #define IMX7D_I2C2_ROOT_DIV 217 231*4882a593Smuzhiyun #define IMX7D_I2C3_ROOT_CLK 218 232*4882a593Smuzhiyun #define IMX7D_I2C3_ROOT_SRC 219 233*4882a593Smuzhiyun #define IMX7D_I2C3_ROOT_CG 220 234*4882a593Smuzhiyun #define IMX7D_I2C3_ROOT_DIV 221 235*4882a593Smuzhiyun #define IMX7D_I2C4_ROOT_CLK 222 236*4882a593Smuzhiyun #define IMX7D_I2C4_ROOT_SRC 223 237*4882a593Smuzhiyun #define IMX7D_I2C4_ROOT_CG 224 238*4882a593Smuzhiyun #define IMX7D_I2C4_ROOT_DIV 225 239*4882a593Smuzhiyun #define IMX7D_UART1_ROOT_CLK 226 240*4882a593Smuzhiyun #define IMX7D_UART1_ROOT_SRC 227 241*4882a593Smuzhiyun #define IMX7D_UART1_ROOT_CG 228 242*4882a593Smuzhiyun #define IMX7D_UART1_ROOT_DIV 229 243*4882a593Smuzhiyun #define IMX7D_UART2_ROOT_CLK 230 244*4882a593Smuzhiyun #define IMX7D_UART2_ROOT_SRC 231 245*4882a593Smuzhiyun #define IMX7D_UART2_ROOT_CG 232 246*4882a593Smuzhiyun #define IMX7D_UART2_ROOT_DIV 233 247*4882a593Smuzhiyun #define IMX7D_UART3_ROOT_CLK 234 248*4882a593Smuzhiyun #define IMX7D_UART3_ROOT_SRC 235 249*4882a593Smuzhiyun #define IMX7D_UART3_ROOT_CG 236 250*4882a593Smuzhiyun #define IMX7D_UART3_ROOT_DIV 237 251*4882a593Smuzhiyun #define IMX7D_UART4_ROOT_CLK 238 252*4882a593Smuzhiyun #define IMX7D_UART4_ROOT_SRC 239 253*4882a593Smuzhiyun #define IMX7D_UART4_ROOT_CG 240 254*4882a593Smuzhiyun #define IMX7D_UART4_ROOT_DIV 241 255*4882a593Smuzhiyun #define IMX7D_UART5_ROOT_CLK 242 256*4882a593Smuzhiyun #define IMX7D_UART5_ROOT_SRC 243 257*4882a593Smuzhiyun #define IMX7D_UART5_ROOT_CG 244 258*4882a593Smuzhiyun #define IMX7D_UART5_ROOT_DIV 245 259*4882a593Smuzhiyun #define IMX7D_UART6_ROOT_CLK 246 260*4882a593Smuzhiyun #define IMX7D_UART6_ROOT_SRC 247 261*4882a593Smuzhiyun #define IMX7D_UART6_ROOT_CG 248 262*4882a593Smuzhiyun #define IMX7D_UART6_ROOT_DIV 249 263*4882a593Smuzhiyun #define IMX7D_UART7_ROOT_CLK 250 264*4882a593Smuzhiyun #define IMX7D_UART7_ROOT_SRC 251 265*4882a593Smuzhiyun #define IMX7D_UART7_ROOT_CG 252 266*4882a593Smuzhiyun #define IMX7D_UART7_ROOT_DIV 253 267*4882a593Smuzhiyun #define IMX7D_ECSPI1_ROOT_CLK 254 268*4882a593Smuzhiyun #define IMX7D_ECSPI1_ROOT_SRC 255 269*4882a593Smuzhiyun #define IMX7D_ECSPI1_ROOT_CG 256 270*4882a593Smuzhiyun #define IMX7D_ECSPI1_ROOT_DIV 257 271*4882a593Smuzhiyun #define IMX7D_ECSPI2_ROOT_CLK 258 272*4882a593Smuzhiyun #define IMX7D_ECSPI2_ROOT_SRC 259 273*4882a593Smuzhiyun #define IMX7D_ECSPI2_ROOT_CG 260 274*4882a593Smuzhiyun #define IMX7D_ECSPI2_ROOT_DIV 261 275*4882a593Smuzhiyun #define IMX7D_ECSPI3_ROOT_CLK 262 276*4882a593Smuzhiyun #define IMX7D_ECSPI3_ROOT_SRC 263 277*4882a593Smuzhiyun #define IMX7D_ECSPI3_ROOT_CG 264 278*4882a593Smuzhiyun #define IMX7D_ECSPI3_ROOT_DIV 265 279*4882a593Smuzhiyun #define IMX7D_ECSPI4_ROOT_CLK 266 280*4882a593Smuzhiyun #define IMX7D_ECSPI4_ROOT_SRC 267 281*4882a593Smuzhiyun #define IMX7D_ECSPI4_ROOT_CG 268 282*4882a593Smuzhiyun #define IMX7D_ECSPI4_ROOT_DIV 269 283*4882a593Smuzhiyun #define IMX7D_PWM1_ROOT_CLK 270 284*4882a593Smuzhiyun #define IMX7D_PWM1_ROOT_SRC 271 285*4882a593Smuzhiyun #define IMX7D_PWM1_ROOT_CG 272 286*4882a593Smuzhiyun #define IMX7D_PWM1_ROOT_DIV 273 287*4882a593Smuzhiyun #define IMX7D_PWM2_ROOT_CLK 274 288*4882a593Smuzhiyun #define IMX7D_PWM2_ROOT_SRC 275 289*4882a593Smuzhiyun #define IMX7D_PWM2_ROOT_CG 276 290*4882a593Smuzhiyun #define IMX7D_PWM2_ROOT_DIV 277 291*4882a593Smuzhiyun #define IMX7D_PWM3_ROOT_CLK 278 292*4882a593Smuzhiyun #define IMX7D_PWM3_ROOT_SRC 279 293*4882a593Smuzhiyun #define IMX7D_PWM3_ROOT_CG 280 294*4882a593Smuzhiyun #define IMX7D_PWM3_ROOT_DIV 281 295*4882a593Smuzhiyun #define IMX7D_PWM4_ROOT_CLK 282 296*4882a593Smuzhiyun #define IMX7D_PWM4_ROOT_SRC 283 297*4882a593Smuzhiyun #define IMX7D_PWM4_ROOT_CG 284 298*4882a593Smuzhiyun #define IMX7D_PWM4_ROOT_DIV 285 299*4882a593Smuzhiyun #define IMX7D_FLEXTIMER1_ROOT_CLK 286 300*4882a593Smuzhiyun #define IMX7D_FLEXTIMER1_ROOT_SRC 287 301*4882a593Smuzhiyun #define IMX7D_FLEXTIMER1_ROOT_CG 288 302*4882a593Smuzhiyun #define IMX7D_FLEXTIMER1_ROOT_DIV 289 303*4882a593Smuzhiyun #define IMX7D_FLEXTIMER2_ROOT_CLK 290 304*4882a593Smuzhiyun #define IMX7D_FLEXTIMER2_ROOT_SRC 291 305*4882a593Smuzhiyun #define IMX7D_FLEXTIMER2_ROOT_CG 292 306*4882a593Smuzhiyun #define IMX7D_FLEXTIMER2_ROOT_DIV 293 307*4882a593Smuzhiyun #define IMX7D_SIM1_ROOT_CLK 294 308*4882a593Smuzhiyun #define IMX7D_SIM1_ROOT_SRC 295 309*4882a593Smuzhiyun #define IMX7D_SIM1_ROOT_CG 296 310*4882a593Smuzhiyun #define IMX7D_SIM1_ROOT_DIV 297 311*4882a593Smuzhiyun #define IMX7D_SIM2_ROOT_CLK 298 312*4882a593Smuzhiyun #define IMX7D_SIM2_ROOT_SRC 299 313*4882a593Smuzhiyun #define IMX7D_SIM2_ROOT_CG 300 314*4882a593Smuzhiyun #define IMX7D_SIM2_ROOT_DIV 301 315*4882a593Smuzhiyun #define IMX7D_GPT1_ROOT_CLK 302 316*4882a593Smuzhiyun #define IMX7D_GPT1_ROOT_SRC 303 317*4882a593Smuzhiyun #define IMX7D_GPT1_ROOT_CG 304 318*4882a593Smuzhiyun #define IMX7D_GPT1_ROOT_DIV 305 319*4882a593Smuzhiyun #define IMX7D_GPT2_ROOT_CLK 306 320*4882a593Smuzhiyun #define IMX7D_GPT2_ROOT_SRC 307 321*4882a593Smuzhiyun #define IMX7D_GPT2_ROOT_CG 308 322*4882a593Smuzhiyun #define IMX7D_GPT2_ROOT_DIV 309 323*4882a593Smuzhiyun #define IMX7D_GPT3_ROOT_CLK 310 324*4882a593Smuzhiyun #define IMX7D_GPT3_ROOT_SRC 311 325*4882a593Smuzhiyun #define IMX7D_GPT3_ROOT_CG 312 326*4882a593Smuzhiyun #define IMX7D_GPT3_ROOT_DIV 313 327*4882a593Smuzhiyun #define IMX7D_GPT4_ROOT_CLK 314 328*4882a593Smuzhiyun #define IMX7D_GPT4_ROOT_SRC 315 329*4882a593Smuzhiyun #define IMX7D_GPT4_ROOT_CG 316 330*4882a593Smuzhiyun #define IMX7D_GPT4_ROOT_DIV 317 331*4882a593Smuzhiyun #define IMX7D_TRACE_ROOT_CLK 318 332*4882a593Smuzhiyun #define IMX7D_TRACE_ROOT_SRC 319 333*4882a593Smuzhiyun #define IMX7D_TRACE_ROOT_CG 320 334*4882a593Smuzhiyun #define IMX7D_TRACE_ROOT_DIV 321 335*4882a593Smuzhiyun #define IMX7D_WDOG1_ROOT_CLK 322 336*4882a593Smuzhiyun #define IMX7D_WDOG_ROOT_SRC 323 337*4882a593Smuzhiyun #define IMX7D_WDOG_ROOT_CG 324 338*4882a593Smuzhiyun #define IMX7D_WDOG_ROOT_DIV 325 339*4882a593Smuzhiyun #define IMX7D_CSI_MCLK_ROOT_CLK 326 340*4882a593Smuzhiyun #define IMX7D_CSI_MCLK_ROOT_SRC 327 341*4882a593Smuzhiyun #define IMX7D_CSI_MCLK_ROOT_CG 328 342*4882a593Smuzhiyun #define IMX7D_CSI_MCLK_ROOT_DIV 329 343*4882a593Smuzhiyun #define IMX7D_AUDIO_MCLK_ROOT_CLK 330 344*4882a593Smuzhiyun #define IMX7D_AUDIO_MCLK_ROOT_SRC 331 345*4882a593Smuzhiyun #define IMX7D_AUDIO_MCLK_ROOT_CG 332 346*4882a593Smuzhiyun #define IMX7D_AUDIO_MCLK_ROOT_DIV 333 347*4882a593Smuzhiyun #define IMX7D_WRCLK_ROOT_CLK 334 348*4882a593Smuzhiyun #define IMX7D_WRCLK_ROOT_SRC 335 349*4882a593Smuzhiyun #define IMX7D_WRCLK_ROOT_CG 336 350*4882a593Smuzhiyun #define IMX7D_WRCLK_ROOT_DIV 337 351*4882a593Smuzhiyun #define IMX7D_CLKO1_ROOT_SRC 338 352*4882a593Smuzhiyun #define IMX7D_CLKO1_ROOT_CG 339 353*4882a593Smuzhiyun #define IMX7D_CLKO1_ROOT_DIV 340 354*4882a593Smuzhiyun #define IMX7D_CLKO2_ROOT_SRC 341 355*4882a593Smuzhiyun #define IMX7D_CLKO2_ROOT_CG 342 356*4882a593Smuzhiyun #define IMX7D_CLKO2_ROOT_DIV 343 357*4882a593Smuzhiyun #define IMX7D_MAIN_AXI_ROOT_PRE_DIV 344 358*4882a593Smuzhiyun #define IMX7D_DISP_AXI_ROOT_PRE_DIV 345 359*4882a593Smuzhiyun #define IMX7D_ENET_AXI_ROOT_PRE_DIV 346 360*4882a593Smuzhiyun #define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347 361*4882a593Smuzhiyun #define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 348 362*4882a593Smuzhiyun #define IMX7D_USB_HSIC_ROOT_PRE_DIV 349 363*4882a593Smuzhiyun #define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 350 364*4882a593Smuzhiyun #define IMX7D_PCIE_PHY_ROOT_PRE_DIV 351 365*4882a593Smuzhiyun #define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 352 366*4882a593Smuzhiyun #define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 353 367*4882a593Smuzhiyun #define IMX7D_MIPI_DSI_ROOT_PRE_DIV 354 368*4882a593Smuzhiyun #define IMX7D_MIPI_CSI_ROOT_PRE_DIV 355 369*4882a593Smuzhiyun #define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 356 370*4882a593Smuzhiyun #define IMX7D_SAI1_ROOT_PRE_DIV 357 371*4882a593Smuzhiyun #define IMX7D_SAI2_ROOT_PRE_DIV 358 372*4882a593Smuzhiyun #define IMX7D_SAI3_ROOT_PRE_DIV 359 373*4882a593Smuzhiyun #define IMX7D_SPDIF_ROOT_PRE_DIV 360 374*4882a593Smuzhiyun #define IMX7D_ENET1_REF_ROOT_PRE_DIV 361 375*4882a593Smuzhiyun #define IMX7D_ENET1_TIME_ROOT_PRE_DIV 362 376*4882a593Smuzhiyun #define IMX7D_ENET2_REF_ROOT_PRE_DIV 363 377*4882a593Smuzhiyun #define IMX7D_ENET2_TIME_ROOT_PRE_DIV 364 378*4882a593Smuzhiyun #define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365 379*4882a593Smuzhiyun #define IMX7D_EIM_ROOT_PRE_DIV 366 380*4882a593Smuzhiyun #define IMX7D_NAND_ROOT_PRE_DIV 367 381*4882a593Smuzhiyun #define IMX7D_QSPI_ROOT_PRE_DIV 368 382*4882a593Smuzhiyun #define IMX7D_USDHC1_ROOT_PRE_DIV 369 383*4882a593Smuzhiyun #define IMX7D_USDHC2_ROOT_PRE_DIV 370 384*4882a593Smuzhiyun #define IMX7D_USDHC3_ROOT_PRE_DIV 371 385*4882a593Smuzhiyun #define IMX7D_CAN1_ROOT_PRE_DIV 372 386*4882a593Smuzhiyun #define IMX7D_CAN2_ROOT_PRE_DIV 373 387*4882a593Smuzhiyun #define IMX7D_I2C1_ROOT_PRE_DIV 374 388*4882a593Smuzhiyun #define IMX7D_I2C2_ROOT_PRE_DIV 375 389*4882a593Smuzhiyun #define IMX7D_I2C3_ROOT_PRE_DIV 376 390*4882a593Smuzhiyun #define IMX7D_I2C4_ROOT_PRE_DIV 377 391*4882a593Smuzhiyun #define IMX7D_UART1_ROOT_PRE_DIV 378 392*4882a593Smuzhiyun #define IMX7D_UART2_ROOT_PRE_DIV 379 393*4882a593Smuzhiyun #define IMX7D_UART3_ROOT_PRE_DIV 380 394*4882a593Smuzhiyun #define IMX7D_UART4_ROOT_PRE_DIV 381 395*4882a593Smuzhiyun #define IMX7D_UART5_ROOT_PRE_DIV 382 396*4882a593Smuzhiyun #define IMX7D_UART6_ROOT_PRE_DIV 383 397*4882a593Smuzhiyun #define IMX7D_UART7_ROOT_PRE_DIV 384 398*4882a593Smuzhiyun #define IMX7D_ECSPI1_ROOT_PRE_DIV 385 399*4882a593Smuzhiyun #define IMX7D_ECSPI2_ROOT_PRE_DIV 386 400*4882a593Smuzhiyun #define IMX7D_ECSPI3_ROOT_PRE_DIV 387 401*4882a593Smuzhiyun #define IMX7D_ECSPI4_ROOT_PRE_DIV 388 402*4882a593Smuzhiyun #define IMX7D_PWM1_ROOT_PRE_DIV 389 403*4882a593Smuzhiyun #define IMX7D_PWM2_ROOT_PRE_DIV 390 404*4882a593Smuzhiyun #define IMX7D_PWM3_ROOT_PRE_DIV 391 405*4882a593Smuzhiyun #define IMX7D_PWM4_ROOT_PRE_DIV 392 406*4882a593Smuzhiyun #define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 393 407*4882a593Smuzhiyun #define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 394 408*4882a593Smuzhiyun #define IMX7D_SIM1_ROOT_PRE_DIV 395 409*4882a593Smuzhiyun #define IMX7D_SIM2_ROOT_PRE_DIV 396 410*4882a593Smuzhiyun #define IMX7D_GPT1_ROOT_PRE_DIV 397 411*4882a593Smuzhiyun #define IMX7D_GPT2_ROOT_PRE_DIV 398 412*4882a593Smuzhiyun #define IMX7D_GPT3_ROOT_PRE_DIV 399 413*4882a593Smuzhiyun #define IMX7D_GPT4_ROOT_PRE_DIV 400 414*4882a593Smuzhiyun #define IMX7D_TRACE_ROOT_PRE_DIV 401 415*4882a593Smuzhiyun #define IMX7D_WDOG_ROOT_PRE_DIV 402 416*4882a593Smuzhiyun #define IMX7D_CSI_MCLK_ROOT_PRE_DIV 403 417*4882a593Smuzhiyun #define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 404 418*4882a593Smuzhiyun #define IMX7D_WRCLK_ROOT_PRE_DIV 405 419*4882a593Smuzhiyun #define IMX7D_CLKO1_ROOT_PRE_DIV 406 420*4882a593Smuzhiyun #define IMX7D_CLKO2_ROOT_PRE_DIV 407 421*4882a593Smuzhiyun #define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408 422*4882a593Smuzhiyun #define IMX7D_DRAM_ALT_ROOT_PRE_DIV 409 423*4882a593Smuzhiyun #define IMX7D_LVDS1_IN_CLK 410 424*4882a593Smuzhiyun #define IMX7D_LVDS1_OUT_SEL 411 425*4882a593Smuzhiyun #define IMX7D_LVDS1_OUT_CLK 412 426*4882a593Smuzhiyun #define IMX7D_CLK_DUMMY 413 427*4882a593Smuzhiyun #define IMX7D_GPT_3M_CLK 414 428*4882a593Smuzhiyun #define IMX7D_OCRAM_CLK 415 429*4882a593Smuzhiyun #define IMX7D_OCRAM_S_CLK 416 430*4882a593Smuzhiyun #define IMX7D_WDOG2_ROOT_CLK 417 431*4882a593Smuzhiyun #define IMX7D_WDOG3_ROOT_CLK 418 432*4882a593Smuzhiyun #define IMX7D_WDOG4_ROOT_CLK 419 433*4882a593Smuzhiyun #define IMX7D_SDMA_CORE_CLK 420 434*4882a593Smuzhiyun #define IMX7D_USB1_MAIN_480M_CLK 421 435*4882a593Smuzhiyun #define IMX7D_USB_CTRL_CLK 422 436*4882a593Smuzhiyun #define IMX7D_USB_PHY1_CLK 423 437*4882a593Smuzhiyun #define IMX7D_USB_PHY2_CLK 424 438*4882a593Smuzhiyun #define IMX7D_IPG_ROOT_CLK 425 439*4882a593Smuzhiyun #define IMX7D_SAI1_IPG_CLK 426 440*4882a593Smuzhiyun #define IMX7D_SAI2_IPG_CLK 427 441*4882a593Smuzhiyun #define IMX7D_SAI3_IPG_CLK 428 442*4882a593Smuzhiyun #define IMX7D_PLL_AUDIO_TEST_DIV 429 443*4882a593Smuzhiyun #define IMX7D_PLL_AUDIO_POST_DIV 430 444*4882a593Smuzhiyun #define IMX7D_PLL_VIDEO_TEST_DIV 431 445*4882a593Smuzhiyun #define IMX7D_PLL_VIDEO_POST_DIV 432 446*4882a593Smuzhiyun #define IMX7D_MU_ROOT_CLK 433 447*4882a593Smuzhiyun #define IMX7D_SEMA4_HS_ROOT_CLK 434 448*4882a593Smuzhiyun #define IMX7D_PLL_DRAM_TEST_DIV 435 449*4882a593Smuzhiyun #define IMX7D_ADC_ROOT_CLK 436 450*4882a593Smuzhiyun #define IMX7D_CLK_ARM 437 451*4882a593Smuzhiyun #define IMX7D_CKIL 438 452*4882a593Smuzhiyun #define IMX7D_OCOTP_CLK 439 453*4882a593Smuzhiyun #define IMX7D_CLK_END 440 454*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ 455