1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * GXBB clock tree IDs 3*4882a593Smuzhiyun */ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #ifndef __GXBB_CLKC_H 6*4882a593Smuzhiyun #define __GXBB_CLKC_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define CLKID_HDMI_PLL 2 9*4882a593Smuzhiyun #define CLKID_FCLK_DIV2 4 10*4882a593Smuzhiyun #define CLKID_FCLK_DIV3 5 11*4882a593Smuzhiyun #define CLKID_FCLK_DIV4 6 12*4882a593Smuzhiyun #define CLKID_GP0_PLL 9 13*4882a593Smuzhiyun #define CLKID_CLK81 12 14*4882a593Smuzhiyun #define CLKID_MPLL2 15 15*4882a593Smuzhiyun #define CLKID_SPICC 21 16*4882a593Smuzhiyun #define CLKID_I2C 22 17*4882a593Smuzhiyun #define CLKID_SAR_ADC 23 18*4882a593Smuzhiyun #define CLKID_RNG0 25 19*4882a593Smuzhiyun #define CLKID_UART0 26 20*4882a593Smuzhiyun #define CLKID_SPI 34 21*4882a593Smuzhiyun #define CLKID_ETH 36 22*4882a593Smuzhiyun #define CLKID_AIU_GLUE 38 23*4882a593Smuzhiyun #define CLKID_IEC958 39 24*4882a593Smuzhiyun #define CLKID_I2S_OUT 40 25*4882a593Smuzhiyun #define CLKID_MIXER_IFACE 44 26*4882a593Smuzhiyun #define CLKID_AIU 47 27*4882a593Smuzhiyun #define CLKID_UART1 48 28*4882a593Smuzhiyun #define CLKID_USB0 50 29*4882a593Smuzhiyun #define CLKID_USB1 51 30*4882a593Smuzhiyun #define CLKID_USB 55 31*4882a593Smuzhiyun #define CLKID_HDMI_PCLK 63 32*4882a593Smuzhiyun #define CLKID_USB1_DDR_BRIDGE 64 33*4882a593Smuzhiyun #define CLKID_USB0_DDR_BRIDGE 65 34*4882a593Smuzhiyun #define CLKID_UART2 68 35*4882a593Smuzhiyun #define CLKID_SANA 69 36*4882a593Smuzhiyun #define CLKID_GCLK_VENCI_INT0 77 37*4882a593Smuzhiyun #define CLKID_AOCLK_GATE 80 38*4882a593Smuzhiyun #define CLKID_IEC958_GATE 81 39*4882a593Smuzhiyun #define CLKID_AO_I2C 93 40*4882a593Smuzhiyun #define CLKID_SD_EMMC_A 94 41*4882a593Smuzhiyun #define CLKID_SD_EMMC_B 95 42*4882a593Smuzhiyun #define CLKID_SD_EMMC_C 96 43*4882a593Smuzhiyun #define CLKID_SAR_ADC_CLK 97 44*4882a593Smuzhiyun #define CLKID_SAR_ADC_SEL 98 45*4882a593Smuzhiyun #define CLKID_MALI_0_SEL 100 46*4882a593Smuzhiyun #define CLKID_MALI_0 102 47*4882a593Smuzhiyun #define CLKID_MALI_1_SEL 103 48*4882a593Smuzhiyun #define CLKID_MALI_1 105 49*4882a593Smuzhiyun #define CLKID_MALI 106 50*4882a593Smuzhiyun #define CLKID_CTS_AMCLK 107 51*4882a593Smuzhiyun #define CLKID_CTS_MCLK_I958 110 52*4882a593Smuzhiyun #define CLKID_CTS_I958 113 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #endif /* __GXBB_CLKC_H */ 55