1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_BCM63268_H 10*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_BCM63268_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define BCM63268_CLK_GLESS 0 13*4882a593Smuzhiyun #define BCM63268_CLK_VDSL_QPROC 1 14*4882a593Smuzhiyun #define BCM63268_CLK_VDSL_AFE 2 15*4882a593Smuzhiyun #define BCM63268_CLK_VDSL 3 16*4882a593Smuzhiyun #define BCM63268_CLK_MIPS 4 17*4882a593Smuzhiyun #define BCM63268_CLK_WLAN_OCP 5 18*4882a593Smuzhiyun #define BCM63268_CLK_DECT 6 19*4882a593Smuzhiyun #define BCM63268_CLK_FAP0 7 20*4882a593Smuzhiyun #define BCM63268_CLK_FAP1 8 21*4882a593Smuzhiyun #define BCM63268_CLK_SAR 9 22*4882a593Smuzhiyun #define BCM63268_CLK_ROBOSW 10 23*4882a593Smuzhiyun #define BCM63268_CLK_PCM 11 24*4882a593Smuzhiyun #define BCM63268_CLK_USBD 12 25*4882a593Smuzhiyun #define BCM63268_CLK_USBH 13 26*4882a593Smuzhiyun #define BCM63268_CLK_IPSEC 14 27*4882a593Smuzhiyun #define BCM63268_CLK_SPI 15 28*4882a593Smuzhiyun #define BCM63268_CLK_HSSPI 16 29*4882a593Smuzhiyun #define BCM63268_CLK_PCIE 17 30*4882a593Smuzhiyun #define BCM63268_CLK_PHYMIPS 18 31*4882a593Smuzhiyun #define BCM63268_CLK_GMAC 19 32*4882a593Smuzhiyun #define BCM63268_CLK_NAND 20 33*4882a593Smuzhiyun #define BCM63268_CLK_TBUS 27 34*4882a593Smuzhiyun #define BCM63268_CLK_ROBOSW250 31 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define BCM63268_TCLK_EPHY1 0 37*4882a593Smuzhiyun #define BCM63268_TCLK_EPHY2 1 38*4882a593Smuzhiyun #define BCM63268_TCLK_EPHY3 2 39*4882a593Smuzhiyun #define BCM63268_TCLK_GPHY 3 40*4882a593Smuzhiyun #define BCM63268_TCLK_DSL 4 41*4882a593Smuzhiyun #define BCM63268_TCLK_WO_EPHY 5 42*4882a593Smuzhiyun #define BCM63268_TCLK_WO_DSL 6 43*4882a593Smuzhiyun #define BCM63268_TCLK_FAP1 11 44*4882a593Smuzhiyun #define BCM63268_TCLK_FAP2 15 45*4882a593Smuzhiyun #define BCM63268_TCLK_UTO_50 16 46*4882a593Smuzhiyun #define BCM63268_TCLK_UTO_EXT 17 47*4882a593Smuzhiyun #define BCM63268_TCLK_USB_REF 18 48*4882a593Smuzhiyun #define BCM63268_TCLK_SW_RST 29 49*4882a593Smuzhiyun #define BCM63268_TCLK_HW_RST 30 50*4882a593Smuzhiyun #define BCM63268_TCLK_POR_RST 31 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_BCM63268_H */ 53