1 /* SPDX-License-Identifier: MIT 2 * Copyright (C) 2018 Intel Corp. 3 * 4 * Authors: 5 * Manasi Navare <manasi.d.navare@intel.com> 6 */ 7 8 #ifndef DRM_DSC_H_ 9 #define DRM_DSC_H_ 10 11 #include <common.h> 12 #include <drm/drm_dp_helper.h> 13 14 /* VESA Display Stream Compression DSC 1.2 constants */ 15 #define DSC_NUM_BUF_RANGES 15 16 #define DSC_MUX_WORD_SIZE_8_10_BPC 48 17 #define DSC_MUX_WORD_SIZE_12_BPC 64 18 #define DSC_RC_PIXELS_PER_GROUP 3 19 #define DSC_SCALE_DECREMENT_INTERVAL_MAX 4095 20 #define DSC_RANGE_BPG_OFFSET_MASK 0x3f 21 22 /* DSC Rate Control Constants */ 23 #define DSC_RC_MODEL_SIZE_CONST 8192 24 #define DSC_RC_EDGE_FACTOR_CONST 6 25 #define DSC_RC_TGT_OFFSET_HI_CONST 3 26 #define DSC_RC_TGT_OFFSET_LO_CONST 3 27 28 /* DSC PPS constants and macros */ 29 #define DSC_PPS_VERSION_MAJOR_SHIFT 4 30 #define DSC_PPS_BPC_SHIFT 4 31 #define DSC_PPS_MSB_SHIFT 8 32 #define DSC_PPS_LSB_MASK (0xFF << 0) 33 #define DSC_PPS_BPP_HIGH_MASK (0x3 << 8) 34 #define DSC_PPS_VBR_EN_SHIFT 2 35 #define DSC_PPS_SIMPLE422_SHIFT 3 36 #define DSC_PPS_CONVERT_RGB_SHIFT 4 37 #define DSC_PPS_BLOCK_PRED_EN_SHIFT 5 38 #define DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK (0x3 << 8) 39 #define DSC_PPS_SCALE_DEC_INT_HIGH_MASK (0xF << 8) 40 #define DSC_PPS_RC_TGT_OFFSET_HI_SHIFT 4 41 #define DSC_PPS_RC_RANGE_MINQP_SHIFT 11 42 #define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6 43 #define DSC_PPS_NATIVE_420_SHIFT 1 44 #define DSC_1_2_MAX_LINEBUF_DEPTH_BITS 16 45 #define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0 46 #define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13 47 48 /** 49 * struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters 50 * 51 * This defines different rate control parameters used by the DSC engine 52 * to compress the frame. 53 */ 54 struct drm_dsc_rc_range_parameters { 55 /** 56 * @range_min_qp: Min Quantization Parameters allowed for this range 57 */ 58 u8 range_min_qp; 59 /** 60 * @range_max_qp: Max Quantization Parameters allowed for this range 61 */ 62 u8 range_max_qp; 63 /** 64 * @range_bpg_offset: 65 * Bits/group offset to apply to target for this group 66 */ 67 u8 range_bpg_offset; 68 }; 69 70 /** 71 * struct drm_dsc_config - Parameters required to configure DSC 72 * 73 * Driver populates this structure with all the parameters required 74 * to configure the display stream compression on the source. 75 */ 76 struct drm_dsc_config { 77 /** 78 * @line_buf_depth: 79 * Bits per component for previous reconstructed line buffer 80 */ 81 u8 line_buf_depth; 82 /** 83 * @bits_per_component: Bits per component to code (8/10/12) 84 */ 85 u8 bits_per_component; 86 /** 87 * @convert_rgb: 88 * Flag to indicate if RGB - YCoCg conversion is needed 89 * True if RGB input, False if YCoCg input 90 */ 91 bool convert_rgb; 92 /** 93 * @slice_count: Number of slices per line used by the DSC encoder 94 */ 95 u8 slice_count; 96 /** 97 * @slice_width: Width of each slice in pixels 98 */ 99 u16 slice_width; 100 /** 101 * @slice_height: Slice height in pixels 102 */ 103 u16 slice_height; 104 /** 105 * @simple_422: True if simple 4_2_2 mode is enabled else False 106 */ 107 bool simple_422; 108 /** 109 * @pic_width: Width of the input display frame in pixels 110 */ 111 u16 pic_width; 112 /** 113 * @pic_height: Vertical height of the input display frame 114 */ 115 u16 pic_height; 116 /** 117 * @rc_tgt_offset_high: 118 * Offset to bits/group used by RC to determine QP adjustment 119 */ 120 u8 rc_tgt_offset_high; 121 /** 122 * @rc_tgt_offset_low: 123 * Offset to bits/group used by RC to determine QP adjustment 124 */ 125 u8 rc_tgt_offset_low; 126 /** 127 * @bits_per_pixel: 128 * Target bits per pixel with 4 fractional bits, bits_per_pixel << 4 129 */ 130 u16 bits_per_pixel; 131 /** 132 * @rc_edge_factor: 133 * Factor to determine if an edge is present based on the bits produced 134 */ 135 u8 rc_edge_factor; 136 /** 137 * @rc_quant_incr_limit1: 138 * Slow down incrementing once the range reaches this value 139 */ 140 u8 rc_quant_incr_limit1; 141 /** 142 * @rc_quant_incr_limit0: 143 * Slow down incrementing once the range reaches this value 144 */ 145 u8 rc_quant_incr_limit0; 146 /** 147 * @initial_xmit_delay: 148 * Number of pixels to delay the initial transmission 149 */ 150 u16 initial_xmit_delay; 151 /** 152 * @initial_dec_delay: 153 * Initial decoder delay, number of pixel times that the decoder 154 * accumulates data in its rate buffer before starting to decode 155 * and output pixels. 156 */ 157 u16 initial_dec_delay; 158 /** 159 * @block_pred_enable: 160 * True if block prediction is used to code any groups within the 161 * picture. False if BP not used 162 */ 163 bool block_pred_enable; 164 /** 165 * @first_line_bpg_offset: 166 * Number of additional bits allocated for each group on the first 167 * line of slice. 168 */ 169 u8 first_line_bpg_offset; 170 /** 171 * @initial_offset: Value to use for RC model offset at slice start 172 */ 173 u16 initial_offset; 174 /** 175 * @rc_buf_thresh: Thresholds defining each of the buffer ranges 176 */ 177 u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1]; 178 /** 179 * @rc_range_params: 180 * Parameters for each of the RC ranges defined in 181 * &struct drm_dsc_rc_range_parameters 182 */ 183 struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; 184 /** 185 * @rc_model_size: Total size of RC model 186 */ 187 u16 rc_model_size; 188 /** 189 * @flatness_min_qp: Minimum QP where flatness information is sent 190 */ 191 u8 flatness_min_qp; 192 /** 193 * @flatness_max_qp: Maximum QP where flatness information is sent 194 */ 195 u8 flatness_max_qp; 196 /** 197 * @initial_scale_value: Initial value for the scale factor 198 */ 199 u8 initial_scale_value; 200 /** 201 * @scale_decrement_interval: 202 * Specifies number of group times between decrementing the scale factor 203 * at beginning of a slice. 204 */ 205 u16 scale_decrement_interval; 206 /** 207 * @scale_increment_interval: 208 * Number of group times between incrementing the scale factor value 209 * used at the beginning of a slice. 210 */ 211 u16 scale_increment_interval; 212 /** 213 * @nfl_bpg_offset: Non first line BPG offset to be used 214 */ 215 u16 nfl_bpg_offset; 216 /** 217 * @slice_bpg_offset: BPG offset used to enforce slice bit 218 */ 219 u16 slice_bpg_offset; 220 /** 221 * @final_offset: Final RC linear transformation offset value 222 */ 223 u16 final_offset; 224 /** 225 * @vbr_enable: True if VBR mode is enabled, false if disabled 226 */ 227 bool vbr_enable; 228 /** 229 * @mux_word_size: Mux word size (in bits) for SSM mode 230 */ 231 u8 mux_word_size; 232 /** 233 * @slice_chunk_size: 234 * The (max) size in bytes of the "chunks" that are used in slice 235 * multiplexing. 236 */ 237 u16 slice_chunk_size; 238 /** 239 * @rc_bits: Rate control buffer size in bits 240 */ 241 u16 rc_bits; 242 /** 243 * @dsc_version_minor: DSC minor version 244 */ 245 u8 dsc_version_minor; 246 /** 247 * @dsc_version_major: DSC major version 248 */ 249 u8 dsc_version_major; 250 /** 251 * @native_422: True if Native 4:2:2 supported, else false 252 */ 253 bool native_422; 254 /** 255 * @native_420: True if Native 4:2:0 supported else false. 256 */ 257 bool native_420; 258 /** 259 * @second_line_bpg_offset: 260 * Additional bits/grp for seconnd line of slice for native 4:2:0 261 */ 262 u8 second_line_bpg_offset; 263 /** 264 * @nsl_bpg_offset: 265 * Num of bits deallocated for each grp that is not in second line of 266 * slice 267 */ 268 u16 nsl_bpg_offset; 269 /** 270 * @second_line_offset_adj: 271 * Offset adjustment for second line in Native 4:2:0 mode 272 */ 273 u16 second_line_offset_adj; 274 }; 275 276 /** 277 * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set 278 * 279 * The VESA DSC standard defines picture parameter set (PPS) which display 280 * stream compression encoders must communicate to decoders. 281 * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in 282 * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2. 283 * The PPS fields that span over more than a byte should be stored in Big Endian 284 * format. 285 */ 286 struct drm_dsc_picture_parameter_set { 287 /** 288 * @dsc_version: 289 * PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC 290 * PPS0[7:4] - dsc_version_major: Contains major version of DSC 291 */ 292 u8 dsc_version; 293 /** 294 * @pps_identifier: 295 * PPS1[7:0] - Application specific identifier that can be 296 * used to differentiate between different PPS tables. 297 */ 298 u8 pps_identifier; 299 /** 300 * @pps_reserved: 301 * PPS2[7:0]- RESERVED Byte 302 */ 303 u8 pps_reserved; 304 /** 305 * @pps_3: 306 * PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to 307 * generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits, 308 * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits, 309 * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2. 310 * PPS3[7:4] - bits_per_component: Bits per component for the original 311 * pixels of the encoded picture. 312 * 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2) 313 * 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also 314 * allowed only when dsc_minor_version = 0x2) 315 */ 316 u8 pps_3; 317 /** 318 * @pps_4: 319 * PPS4[1:0] -These are the most significant 2 bits of 320 * compressed BPP bits_per_pixel[9:0] syntax element. 321 * PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled 322 * PPS4[3] - simple_422: Indicates if decoder drops samples to 323 * reconstruct the 4:2:2 picture. 324 * PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is 325 * active. 326 * PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any 327 * groups in picture 328 * PPS4[7:6] - Reserved bits 329 */ 330 u8 pps_4; 331 /** 332 * @bits_per_pixel_low: 333 * PPS5[7:0] - This indicates the lower significant 8 bits of 334 * the compressed BPP bits_per_pixel[9:0] element. 335 */ 336 u8 bits_per_pixel_low; 337 /** 338 * @pic_height: 339 * PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows 340 * within the raster. 341 */ 342 __be16 pic_height; 343 /** 344 * @pic_width: 345 * PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within 346 * the raster. 347 */ 348 __be16 pic_width; 349 /** 350 * @slice_height: 351 * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels. 352 */ 353 __be16 slice_height; 354 /** 355 * @slice_width: 356 * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels. 357 */ 358 __be16 slice_width; 359 /** 360 * @chunk_size: 361 * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks 362 * that are used for slice multiplexing. 363 */ 364 __be16 chunk_size; 365 /** 366 * @initial_xmit_delay_high: 367 * PPS16[1:0] - Most Significant two bits of initial transmission delay. 368 * It specifies the number of pixel times that the encoder waits before 369 * transmitting data from its rate buffer. 370 * PPS16[7:2] - Reserved 371 */ 372 u8 initial_xmit_delay_high; 373 /** 374 * @initial_xmit_delay_low: 375 * PPS17[7:0] - Least significant 8 bits of initial transmission delay. 376 */ 377 u8 initial_xmit_delay_low; 378 /** 379 * @initial_dec_delay: 380 * 381 * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number 382 * of pixel times that the decoder accumulates data in its rate buffer 383 * before starting to decode and output pixels. 384 */ 385 __be16 initial_dec_delay; 386 /** 387 * @pps20_reserved: 388 * 389 * PPS20[7:0] - Reserved 390 */ 391 u8 pps20_reserved; 392 /** 393 * @initial_scale_value: 394 * PPS21[5:0] - Initial rcXformScale factor used at beginning 395 * of a slice. 396 * PPS21[7:6] - Reserved 397 */ 398 u8 initial_scale_value; 399 /** 400 * @scale_increment_interval: 401 * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing 402 * the rcXformScale factor at end of a slice. 403 */ 404 __be16 scale_increment_interval; 405 /** 406 * @scale_decrement_interval_high: 407 * PPS24[3:0] - Higher 4 bits indicating number of group times between 408 * decrementing the rcXformScale factor at beginning of a slice. 409 * PPS24[7:4] - Reserved 410 */ 411 u8 scale_decrement_interval_high; 412 /** 413 * @scale_decrement_interval_low: 414 * PPS25[7:0] - Lower 8 bits of scale decrement interval 415 */ 416 u8 scale_decrement_interval_low; 417 /** 418 * @pps26_reserved: 419 * PPS26[7:0] 420 */ 421 u8 pps26_reserved; 422 /** 423 * @first_line_bpg_offset: 424 * PPS27[4:0] - Number of additional bits that are allocated 425 * for each group on first line of a slice. 426 * PPS27[7:5] - Reserved 427 */ 428 u8 first_line_bpg_offset; 429 /** 430 * @nfl_bpg_offset: 431 * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits 432 * deallocated for each group for groups after the first line of slice. 433 */ 434 __be16 nfl_bpg_offset; 435 /** 436 * @slice_bpg_offset: 437 * PPS30, PPS31[7:0] - Number of bits that are deallocated for each 438 * group to enforce the slice constraint. 439 */ 440 __be16 slice_bpg_offset; 441 /** 442 * @initial_offset: 443 * PPS32,33[7:0] - Initial value for rcXformOffset 444 */ 445 __be16 initial_offset; 446 /** 447 * @final_offset: 448 * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset 449 */ 450 __be16 final_offset; 451 /** 452 * @flatness_min_qp: 453 * PPS36[4:0] - Minimum QP at which flatness is signaled and 454 * flatness QP adjustment is made. 455 * PPS36[7:5] - Reserved 456 */ 457 u8 flatness_min_qp; 458 /** 459 * @flatness_max_qp: 460 * PPS37[4:0] - Max QP at which flatness is signalled and 461 * the flatness adjustment is made. 462 * PPS37[7:5] - Reserved 463 */ 464 u8 flatness_max_qp; 465 /** 466 * @rc_model_size: 467 * PPS38,39[7:0] - Number of bits within RC Model. 468 */ 469 __be16 rc_model_size; 470 /** 471 * @rc_edge_factor: 472 * PPS40[3:0] - Ratio of current activity vs, previous 473 * activity to determine presence of edge. 474 * PPS40[7:4] - Reserved 475 */ 476 u8 rc_edge_factor; 477 /** 478 * @rc_quant_incr_limit0: 479 * PPS41[4:0] - QP threshold used in short term RC 480 * PPS41[7:5] - Reserved 481 */ 482 u8 rc_quant_incr_limit0; 483 /** 484 * @rc_quant_incr_limit1: 485 * PPS42[4:0] - QP threshold used in short term RC 486 * PPS42[7:5] - Reserved 487 */ 488 u8 rc_quant_incr_limit1; 489 /** 490 * @rc_tgt_offset: 491 * PPS43[3:0] - Lower end of the variability range around the target 492 * bits per group that is allowed by short term RC. 493 * PPS43[7:4]- Upper end of the variability range around the target 494 * bits per group that i allowed by short term rc. 495 */ 496 u8 rc_tgt_offset; 497 /** 498 * @rc_buf_thresh: 499 * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for 500 * the 15 ranges defined by 14 thresholds. 501 */ 502 u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1]; 503 /** 504 * @rc_range_parameters: 505 * PPS58[7:0] - PPS87[7:0] 506 * Parameters that correspond to each of the 15 ranges. 507 */ 508 __be16 rc_range_parameters[DSC_NUM_BUF_RANGES]; 509 /** 510 * @native_422_420: 511 * PPS88[0] - 0 = Native 4:2:2 not used 512 * 1 = Native 4:2:2 used 513 * PPS88[1] - 0 = Native 4:2:0 not use 514 * 1 = Native 4:2:0 used 515 * PPS88[7:2] - Reserved 6 bits 516 */ 517 u8 native_422_420; 518 /** 519 * @second_line_bpg_offset: 520 * PPS89[4:0] - Additional bits/group budget for the 521 * second line of a slice in Native 4:2:0 mode. 522 * Set to 0 if DSC minor version is 1 or native420 is 0. 523 * PPS89[7:5] - Reserved 524 */ 525 u8 second_line_bpg_offset; 526 /** 527 * @nsl_bpg_offset: 528 * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated 529 * for each group that is not in the second line of a slice. 530 */ 531 __be16 nsl_bpg_offset; 532 /** 533 * @second_line_offset_adj: 534 * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second 535 * line in Native 4:2:0 mode. 536 */ 537 __be16 second_line_offset_adj; 538 /** 539 * @pps_long_94_reserved: 540 * PPS 94, 95, 96, 97 - Reserved 541 */ 542 u32 pps_long_94_reserved; 543 /** 544 * @pps_long_98_reserved: 545 * PPS 98, 99, 100, 101 - Reserved 546 */ 547 u32 pps_long_98_reserved; 548 /** 549 * @pps_long_102_reserved: 550 * PPS 102, 103, 104, 105 - Reserved 551 */ 552 u32 pps_long_102_reserved; 553 /** 554 * @pps_long_106_reserved: 555 * PPS 106, 107, 108, 109 - reserved 556 */ 557 u32 pps_long_106_reserved; 558 /** 559 * @pps_long_110_reserved: 560 * PPS 110, 111, 112, 113 - reserved 561 */ 562 u32 pps_long_110_reserved; 563 /** 564 * @pps_long_114_reserved: 565 * PPS 114 - 117 - reserved 566 */ 567 u32 pps_long_114_reserved; 568 /** 569 * @pps_long_118_reserved: 570 * PPS 118 - 121 - reserved 571 */ 572 u32 pps_long_118_reserved; 573 /** 574 * @pps_long_122_reserved: 575 * PPS 122- 125 - reserved 576 */ 577 u32 pps_long_122_reserved; 578 /** 579 * @pps_short_126_reserved: 580 * PPS 126, 127 - reserved 581 */ 582 __be16 pps_short_126_reserved; 583 } __packed; 584 585 /** 586 * struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture Parameter 587 * Set Metadata 588 * 589 * This structure represents the DSC PPS infoframe required to send the Picture 590 * Parameter Set metadata required before enabling VESA Display Stream 591 * Compression. This is based on the DP Secondary Data Packet structure and 592 * comprises of SDP Header as defined &struct dp_sdp_header in drm_dp_helper.h 593 * and PPS payload defined in &struct drm_dsc_picture_parameter_set. 594 * 595 * @pps_header: Header for PPS as per DP SDP header format of type 596 * &struct dp_sdp_header 597 * @pps_payload: PPS payload fields as per DSC specification Table 4-1 598 * as represented in &struct drm_dsc_picture_parameter_set 599 */ 600 struct drm_dsc_pps_infoframe { 601 struct dp_sdp_header pps_header; 602 struct drm_dsc_picture_parameter_set pps_payload; 603 } __packed; 604 605 void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header); 606 void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, 607 const struct drm_dsc_config *dsc_cfg); 608 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); 609 610 #endif /* _DRM_DSC_H_ */ 611