1*4882a593Smuzhiyun /* SPDX-License-Identifier: MIT 2*4882a593Smuzhiyun * Copyright (C) 2018 Intel Corp. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Authors: 5*4882a593Smuzhiyun * Manasi Navare <manasi.d.navare@intel.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef DRM_DSC_H_ 9*4882a593Smuzhiyun #define DRM_DSC_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <common.h> 12*4882a593Smuzhiyun #include <drm/drm_dp_helper.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* VESA Display Stream Compression DSC 1.2 constants */ 15*4882a593Smuzhiyun #define DSC_NUM_BUF_RANGES 15 16*4882a593Smuzhiyun #define DSC_MUX_WORD_SIZE_8_10_BPC 48 17*4882a593Smuzhiyun #define DSC_MUX_WORD_SIZE_12_BPC 64 18*4882a593Smuzhiyun #define DSC_RC_PIXELS_PER_GROUP 3 19*4882a593Smuzhiyun #define DSC_SCALE_DECREMENT_INTERVAL_MAX 4095 20*4882a593Smuzhiyun #define DSC_RANGE_BPG_OFFSET_MASK 0x3f 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* DSC Rate Control Constants */ 23*4882a593Smuzhiyun #define DSC_RC_MODEL_SIZE_CONST 8192 24*4882a593Smuzhiyun #define DSC_RC_EDGE_FACTOR_CONST 6 25*4882a593Smuzhiyun #define DSC_RC_TGT_OFFSET_HI_CONST 3 26*4882a593Smuzhiyun #define DSC_RC_TGT_OFFSET_LO_CONST 3 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* DSC PPS constants and macros */ 29*4882a593Smuzhiyun #define DSC_PPS_VERSION_MAJOR_SHIFT 4 30*4882a593Smuzhiyun #define DSC_PPS_BPC_SHIFT 4 31*4882a593Smuzhiyun #define DSC_PPS_MSB_SHIFT 8 32*4882a593Smuzhiyun #define DSC_PPS_LSB_MASK (0xFF << 0) 33*4882a593Smuzhiyun #define DSC_PPS_BPP_HIGH_MASK (0x3 << 8) 34*4882a593Smuzhiyun #define DSC_PPS_VBR_EN_SHIFT 2 35*4882a593Smuzhiyun #define DSC_PPS_SIMPLE422_SHIFT 3 36*4882a593Smuzhiyun #define DSC_PPS_CONVERT_RGB_SHIFT 4 37*4882a593Smuzhiyun #define DSC_PPS_BLOCK_PRED_EN_SHIFT 5 38*4882a593Smuzhiyun #define DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK (0x3 << 8) 39*4882a593Smuzhiyun #define DSC_PPS_SCALE_DEC_INT_HIGH_MASK (0xF << 8) 40*4882a593Smuzhiyun #define DSC_PPS_RC_TGT_OFFSET_HI_SHIFT 4 41*4882a593Smuzhiyun #define DSC_PPS_RC_RANGE_MINQP_SHIFT 11 42*4882a593Smuzhiyun #define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6 43*4882a593Smuzhiyun #define DSC_PPS_NATIVE_420_SHIFT 1 44*4882a593Smuzhiyun #define DSC_1_2_MAX_LINEBUF_DEPTH_BITS 16 45*4882a593Smuzhiyun #define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0 46*4882a593Smuzhiyun #define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /** 49*4882a593Smuzhiyun * struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters 50*4882a593Smuzhiyun * 51*4882a593Smuzhiyun * This defines different rate control parameters used by the DSC engine 52*4882a593Smuzhiyun * to compress the frame. 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun struct drm_dsc_rc_range_parameters { 55*4882a593Smuzhiyun /** 56*4882a593Smuzhiyun * @range_min_qp: Min Quantization Parameters allowed for this range 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun u8 range_min_qp; 59*4882a593Smuzhiyun /** 60*4882a593Smuzhiyun * @range_max_qp: Max Quantization Parameters allowed for this range 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun u8 range_max_qp; 63*4882a593Smuzhiyun /** 64*4882a593Smuzhiyun * @range_bpg_offset: 65*4882a593Smuzhiyun * Bits/group offset to apply to target for this group 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun u8 range_bpg_offset; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /** 71*4882a593Smuzhiyun * struct drm_dsc_config - Parameters required to configure DSC 72*4882a593Smuzhiyun * 73*4882a593Smuzhiyun * Driver populates this structure with all the parameters required 74*4882a593Smuzhiyun * to configure the display stream compression on the source. 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun struct drm_dsc_config { 77*4882a593Smuzhiyun /** 78*4882a593Smuzhiyun * @line_buf_depth: 79*4882a593Smuzhiyun * Bits per component for previous reconstructed line buffer 80*4882a593Smuzhiyun */ 81*4882a593Smuzhiyun u8 line_buf_depth; 82*4882a593Smuzhiyun /** 83*4882a593Smuzhiyun * @bits_per_component: Bits per component to code (8/10/12) 84*4882a593Smuzhiyun */ 85*4882a593Smuzhiyun u8 bits_per_component; 86*4882a593Smuzhiyun /** 87*4882a593Smuzhiyun * @convert_rgb: 88*4882a593Smuzhiyun * Flag to indicate if RGB - YCoCg conversion is needed 89*4882a593Smuzhiyun * True if RGB input, False if YCoCg input 90*4882a593Smuzhiyun */ 91*4882a593Smuzhiyun bool convert_rgb; 92*4882a593Smuzhiyun /** 93*4882a593Smuzhiyun * @slice_count: Number of slices per line used by the DSC encoder 94*4882a593Smuzhiyun */ 95*4882a593Smuzhiyun u8 slice_count; 96*4882a593Smuzhiyun /** 97*4882a593Smuzhiyun * @slice_width: Width of each slice in pixels 98*4882a593Smuzhiyun */ 99*4882a593Smuzhiyun u16 slice_width; 100*4882a593Smuzhiyun /** 101*4882a593Smuzhiyun * @slice_height: Slice height in pixels 102*4882a593Smuzhiyun */ 103*4882a593Smuzhiyun u16 slice_height; 104*4882a593Smuzhiyun /** 105*4882a593Smuzhiyun * @simple_422: True if simple 4_2_2 mode is enabled else False 106*4882a593Smuzhiyun */ 107*4882a593Smuzhiyun bool simple_422; 108*4882a593Smuzhiyun /** 109*4882a593Smuzhiyun * @pic_width: Width of the input display frame in pixels 110*4882a593Smuzhiyun */ 111*4882a593Smuzhiyun u16 pic_width; 112*4882a593Smuzhiyun /** 113*4882a593Smuzhiyun * @pic_height: Vertical height of the input display frame 114*4882a593Smuzhiyun */ 115*4882a593Smuzhiyun u16 pic_height; 116*4882a593Smuzhiyun /** 117*4882a593Smuzhiyun * @rc_tgt_offset_high: 118*4882a593Smuzhiyun * Offset to bits/group used by RC to determine QP adjustment 119*4882a593Smuzhiyun */ 120*4882a593Smuzhiyun u8 rc_tgt_offset_high; 121*4882a593Smuzhiyun /** 122*4882a593Smuzhiyun * @rc_tgt_offset_low: 123*4882a593Smuzhiyun * Offset to bits/group used by RC to determine QP adjustment 124*4882a593Smuzhiyun */ 125*4882a593Smuzhiyun u8 rc_tgt_offset_low; 126*4882a593Smuzhiyun /** 127*4882a593Smuzhiyun * @bits_per_pixel: 128*4882a593Smuzhiyun * Target bits per pixel with 4 fractional bits, bits_per_pixel << 4 129*4882a593Smuzhiyun */ 130*4882a593Smuzhiyun u16 bits_per_pixel; 131*4882a593Smuzhiyun /** 132*4882a593Smuzhiyun * @rc_edge_factor: 133*4882a593Smuzhiyun * Factor to determine if an edge is present based on the bits produced 134*4882a593Smuzhiyun */ 135*4882a593Smuzhiyun u8 rc_edge_factor; 136*4882a593Smuzhiyun /** 137*4882a593Smuzhiyun * @rc_quant_incr_limit1: 138*4882a593Smuzhiyun * Slow down incrementing once the range reaches this value 139*4882a593Smuzhiyun */ 140*4882a593Smuzhiyun u8 rc_quant_incr_limit1; 141*4882a593Smuzhiyun /** 142*4882a593Smuzhiyun * @rc_quant_incr_limit0: 143*4882a593Smuzhiyun * Slow down incrementing once the range reaches this value 144*4882a593Smuzhiyun */ 145*4882a593Smuzhiyun u8 rc_quant_incr_limit0; 146*4882a593Smuzhiyun /** 147*4882a593Smuzhiyun * @initial_xmit_delay: 148*4882a593Smuzhiyun * Number of pixels to delay the initial transmission 149*4882a593Smuzhiyun */ 150*4882a593Smuzhiyun u16 initial_xmit_delay; 151*4882a593Smuzhiyun /** 152*4882a593Smuzhiyun * @initial_dec_delay: 153*4882a593Smuzhiyun * Initial decoder delay, number of pixel times that the decoder 154*4882a593Smuzhiyun * accumulates data in its rate buffer before starting to decode 155*4882a593Smuzhiyun * and output pixels. 156*4882a593Smuzhiyun */ 157*4882a593Smuzhiyun u16 initial_dec_delay; 158*4882a593Smuzhiyun /** 159*4882a593Smuzhiyun * @block_pred_enable: 160*4882a593Smuzhiyun * True if block prediction is used to code any groups within the 161*4882a593Smuzhiyun * picture. False if BP not used 162*4882a593Smuzhiyun */ 163*4882a593Smuzhiyun bool block_pred_enable; 164*4882a593Smuzhiyun /** 165*4882a593Smuzhiyun * @first_line_bpg_offset: 166*4882a593Smuzhiyun * Number of additional bits allocated for each group on the first 167*4882a593Smuzhiyun * line of slice. 168*4882a593Smuzhiyun */ 169*4882a593Smuzhiyun u8 first_line_bpg_offset; 170*4882a593Smuzhiyun /** 171*4882a593Smuzhiyun * @initial_offset: Value to use for RC model offset at slice start 172*4882a593Smuzhiyun */ 173*4882a593Smuzhiyun u16 initial_offset; 174*4882a593Smuzhiyun /** 175*4882a593Smuzhiyun * @rc_buf_thresh: Thresholds defining each of the buffer ranges 176*4882a593Smuzhiyun */ 177*4882a593Smuzhiyun u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1]; 178*4882a593Smuzhiyun /** 179*4882a593Smuzhiyun * @rc_range_params: 180*4882a593Smuzhiyun * Parameters for each of the RC ranges defined in 181*4882a593Smuzhiyun * &struct drm_dsc_rc_range_parameters 182*4882a593Smuzhiyun */ 183*4882a593Smuzhiyun struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; 184*4882a593Smuzhiyun /** 185*4882a593Smuzhiyun * @rc_model_size: Total size of RC model 186*4882a593Smuzhiyun */ 187*4882a593Smuzhiyun u16 rc_model_size; 188*4882a593Smuzhiyun /** 189*4882a593Smuzhiyun * @flatness_min_qp: Minimum QP where flatness information is sent 190*4882a593Smuzhiyun */ 191*4882a593Smuzhiyun u8 flatness_min_qp; 192*4882a593Smuzhiyun /** 193*4882a593Smuzhiyun * @flatness_max_qp: Maximum QP where flatness information is sent 194*4882a593Smuzhiyun */ 195*4882a593Smuzhiyun u8 flatness_max_qp; 196*4882a593Smuzhiyun /** 197*4882a593Smuzhiyun * @initial_scale_value: Initial value for the scale factor 198*4882a593Smuzhiyun */ 199*4882a593Smuzhiyun u8 initial_scale_value; 200*4882a593Smuzhiyun /** 201*4882a593Smuzhiyun * @scale_decrement_interval: 202*4882a593Smuzhiyun * Specifies number of group times between decrementing the scale factor 203*4882a593Smuzhiyun * at beginning of a slice. 204*4882a593Smuzhiyun */ 205*4882a593Smuzhiyun u16 scale_decrement_interval; 206*4882a593Smuzhiyun /** 207*4882a593Smuzhiyun * @scale_increment_interval: 208*4882a593Smuzhiyun * Number of group times between incrementing the scale factor value 209*4882a593Smuzhiyun * used at the beginning of a slice. 210*4882a593Smuzhiyun */ 211*4882a593Smuzhiyun u16 scale_increment_interval; 212*4882a593Smuzhiyun /** 213*4882a593Smuzhiyun * @nfl_bpg_offset: Non first line BPG offset to be used 214*4882a593Smuzhiyun */ 215*4882a593Smuzhiyun u16 nfl_bpg_offset; 216*4882a593Smuzhiyun /** 217*4882a593Smuzhiyun * @slice_bpg_offset: BPG offset used to enforce slice bit 218*4882a593Smuzhiyun */ 219*4882a593Smuzhiyun u16 slice_bpg_offset; 220*4882a593Smuzhiyun /** 221*4882a593Smuzhiyun * @final_offset: Final RC linear transformation offset value 222*4882a593Smuzhiyun */ 223*4882a593Smuzhiyun u16 final_offset; 224*4882a593Smuzhiyun /** 225*4882a593Smuzhiyun * @vbr_enable: True if VBR mode is enabled, false if disabled 226*4882a593Smuzhiyun */ 227*4882a593Smuzhiyun bool vbr_enable; 228*4882a593Smuzhiyun /** 229*4882a593Smuzhiyun * @mux_word_size: Mux word size (in bits) for SSM mode 230*4882a593Smuzhiyun */ 231*4882a593Smuzhiyun u8 mux_word_size; 232*4882a593Smuzhiyun /** 233*4882a593Smuzhiyun * @slice_chunk_size: 234*4882a593Smuzhiyun * The (max) size in bytes of the "chunks" that are used in slice 235*4882a593Smuzhiyun * multiplexing. 236*4882a593Smuzhiyun */ 237*4882a593Smuzhiyun u16 slice_chunk_size; 238*4882a593Smuzhiyun /** 239*4882a593Smuzhiyun * @rc_bits: Rate control buffer size in bits 240*4882a593Smuzhiyun */ 241*4882a593Smuzhiyun u16 rc_bits; 242*4882a593Smuzhiyun /** 243*4882a593Smuzhiyun * @dsc_version_minor: DSC minor version 244*4882a593Smuzhiyun */ 245*4882a593Smuzhiyun u8 dsc_version_minor; 246*4882a593Smuzhiyun /** 247*4882a593Smuzhiyun * @dsc_version_major: DSC major version 248*4882a593Smuzhiyun */ 249*4882a593Smuzhiyun u8 dsc_version_major; 250*4882a593Smuzhiyun /** 251*4882a593Smuzhiyun * @native_422: True if Native 4:2:2 supported, else false 252*4882a593Smuzhiyun */ 253*4882a593Smuzhiyun bool native_422; 254*4882a593Smuzhiyun /** 255*4882a593Smuzhiyun * @native_420: True if Native 4:2:0 supported else false. 256*4882a593Smuzhiyun */ 257*4882a593Smuzhiyun bool native_420; 258*4882a593Smuzhiyun /** 259*4882a593Smuzhiyun * @second_line_bpg_offset: 260*4882a593Smuzhiyun * Additional bits/grp for seconnd line of slice for native 4:2:0 261*4882a593Smuzhiyun */ 262*4882a593Smuzhiyun u8 second_line_bpg_offset; 263*4882a593Smuzhiyun /** 264*4882a593Smuzhiyun * @nsl_bpg_offset: 265*4882a593Smuzhiyun * Num of bits deallocated for each grp that is not in second line of 266*4882a593Smuzhiyun * slice 267*4882a593Smuzhiyun */ 268*4882a593Smuzhiyun u16 nsl_bpg_offset; 269*4882a593Smuzhiyun /** 270*4882a593Smuzhiyun * @second_line_offset_adj: 271*4882a593Smuzhiyun * Offset adjustment for second line in Native 4:2:0 mode 272*4882a593Smuzhiyun */ 273*4882a593Smuzhiyun u16 second_line_offset_adj; 274*4882a593Smuzhiyun }; 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun /** 277*4882a593Smuzhiyun * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set 278*4882a593Smuzhiyun * 279*4882a593Smuzhiyun * The VESA DSC standard defines picture parameter set (PPS) which display 280*4882a593Smuzhiyun * stream compression encoders must communicate to decoders. 281*4882a593Smuzhiyun * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in 282*4882a593Smuzhiyun * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2. 283*4882a593Smuzhiyun * The PPS fields that span over more than a byte should be stored in Big Endian 284*4882a593Smuzhiyun * format. 285*4882a593Smuzhiyun */ 286*4882a593Smuzhiyun struct drm_dsc_picture_parameter_set { 287*4882a593Smuzhiyun /** 288*4882a593Smuzhiyun * @dsc_version: 289*4882a593Smuzhiyun * PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC 290*4882a593Smuzhiyun * PPS0[7:4] - dsc_version_major: Contains major version of DSC 291*4882a593Smuzhiyun */ 292*4882a593Smuzhiyun u8 dsc_version; 293*4882a593Smuzhiyun /** 294*4882a593Smuzhiyun * @pps_identifier: 295*4882a593Smuzhiyun * PPS1[7:0] - Application specific identifier that can be 296*4882a593Smuzhiyun * used to differentiate between different PPS tables. 297*4882a593Smuzhiyun */ 298*4882a593Smuzhiyun u8 pps_identifier; 299*4882a593Smuzhiyun /** 300*4882a593Smuzhiyun * @pps_reserved: 301*4882a593Smuzhiyun * PPS2[7:0]- RESERVED Byte 302*4882a593Smuzhiyun */ 303*4882a593Smuzhiyun u8 pps_reserved; 304*4882a593Smuzhiyun /** 305*4882a593Smuzhiyun * @pps_3: 306*4882a593Smuzhiyun * PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to 307*4882a593Smuzhiyun * generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits, 308*4882a593Smuzhiyun * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits, 309*4882a593Smuzhiyun * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2. 310*4882a593Smuzhiyun * PPS3[7:4] - bits_per_component: Bits per component for the original 311*4882a593Smuzhiyun * pixels of the encoded picture. 312*4882a593Smuzhiyun * 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2) 313*4882a593Smuzhiyun * 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also 314*4882a593Smuzhiyun * allowed only when dsc_minor_version = 0x2) 315*4882a593Smuzhiyun */ 316*4882a593Smuzhiyun u8 pps_3; 317*4882a593Smuzhiyun /** 318*4882a593Smuzhiyun * @pps_4: 319*4882a593Smuzhiyun * PPS4[1:0] -These are the most significant 2 bits of 320*4882a593Smuzhiyun * compressed BPP bits_per_pixel[9:0] syntax element. 321*4882a593Smuzhiyun * PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled 322*4882a593Smuzhiyun * PPS4[3] - simple_422: Indicates if decoder drops samples to 323*4882a593Smuzhiyun * reconstruct the 4:2:2 picture. 324*4882a593Smuzhiyun * PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is 325*4882a593Smuzhiyun * active. 326*4882a593Smuzhiyun * PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any 327*4882a593Smuzhiyun * groups in picture 328*4882a593Smuzhiyun * PPS4[7:6] - Reserved bits 329*4882a593Smuzhiyun */ 330*4882a593Smuzhiyun u8 pps_4; 331*4882a593Smuzhiyun /** 332*4882a593Smuzhiyun * @bits_per_pixel_low: 333*4882a593Smuzhiyun * PPS5[7:0] - This indicates the lower significant 8 bits of 334*4882a593Smuzhiyun * the compressed BPP bits_per_pixel[9:0] element. 335*4882a593Smuzhiyun */ 336*4882a593Smuzhiyun u8 bits_per_pixel_low; 337*4882a593Smuzhiyun /** 338*4882a593Smuzhiyun * @pic_height: 339*4882a593Smuzhiyun * PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows 340*4882a593Smuzhiyun * within the raster. 341*4882a593Smuzhiyun */ 342*4882a593Smuzhiyun __be16 pic_height; 343*4882a593Smuzhiyun /** 344*4882a593Smuzhiyun * @pic_width: 345*4882a593Smuzhiyun * PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within 346*4882a593Smuzhiyun * the raster. 347*4882a593Smuzhiyun */ 348*4882a593Smuzhiyun __be16 pic_width; 349*4882a593Smuzhiyun /** 350*4882a593Smuzhiyun * @slice_height: 351*4882a593Smuzhiyun * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels. 352*4882a593Smuzhiyun */ 353*4882a593Smuzhiyun __be16 slice_height; 354*4882a593Smuzhiyun /** 355*4882a593Smuzhiyun * @slice_width: 356*4882a593Smuzhiyun * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels. 357*4882a593Smuzhiyun */ 358*4882a593Smuzhiyun __be16 slice_width; 359*4882a593Smuzhiyun /** 360*4882a593Smuzhiyun * @chunk_size: 361*4882a593Smuzhiyun * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks 362*4882a593Smuzhiyun * that are used for slice multiplexing. 363*4882a593Smuzhiyun */ 364*4882a593Smuzhiyun __be16 chunk_size; 365*4882a593Smuzhiyun /** 366*4882a593Smuzhiyun * @initial_xmit_delay_high: 367*4882a593Smuzhiyun * PPS16[1:0] - Most Significant two bits of initial transmission delay. 368*4882a593Smuzhiyun * It specifies the number of pixel times that the encoder waits before 369*4882a593Smuzhiyun * transmitting data from its rate buffer. 370*4882a593Smuzhiyun * PPS16[7:2] - Reserved 371*4882a593Smuzhiyun */ 372*4882a593Smuzhiyun u8 initial_xmit_delay_high; 373*4882a593Smuzhiyun /** 374*4882a593Smuzhiyun * @initial_xmit_delay_low: 375*4882a593Smuzhiyun * PPS17[7:0] - Least significant 8 bits of initial transmission delay. 376*4882a593Smuzhiyun */ 377*4882a593Smuzhiyun u8 initial_xmit_delay_low; 378*4882a593Smuzhiyun /** 379*4882a593Smuzhiyun * @initial_dec_delay: 380*4882a593Smuzhiyun * 381*4882a593Smuzhiyun * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number 382*4882a593Smuzhiyun * of pixel times that the decoder accumulates data in its rate buffer 383*4882a593Smuzhiyun * before starting to decode and output pixels. 384*4882a593Smuzhiyun */ 385*4882a593Smuzhiyun __be16 initial_dec_delay; 386*4882a593Smuzhiyun /** 387*4882a593Smuzhiyun * @pps20_reserved: 388*4882a593Smuzhiyun * 389*4882a593Smuzhiyun * PPS20[7:0] - Reserved 390*4882a593Smuzhiyun */ 391*4882a593Smuzhiyun u8 pps20_reserved; 392*4882a593Smuzhiyun /** 393*4882a593Smuzhiyun * @initial_scale_value: 394*4882a593Smuzhiyun * PPS21[5:0] - Initial rcXformScale factor used at beginning 395*4882a593Smuzhiyun * of a slice. 396*4882a593Smuzhiyun * PPS21[7:6] - Reserved 397*4882a593Smuzhiyun */ 398*4882a593Smuzhiyun u8 initial_scale_value; 399*4882a593Smuzhiyun /** 400*4882a593Smuzhiyun * @scale_increment_interval: 401*4882a593Smuzhiyun * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing 402*4882a593Smuzhiyun * the rcXformScale factor at end of a slice. 403*4882a593Smuzhiyun */ 404*4882a593Smuzhiyun __be16 scale_increment_interval; 405*4882a593Smuzhiyun /** 406*4882a593Smuzhiyun * @scale_decrement_interval_high: 407*4882a593Smuzhiyun * PPS24[3:0] - Higher 4 bits indicating number of group times between 408*4882a593Smuzhiyun * decrementing the rcXformScale factor at beginning of a slice. 409*4882a593Smuzhiyun * PPS24[7:4] - Reserved 410*4882a593Smuzhiyun */ 411*4882a593Smuzhiyun u8 scale_decrement_interval_high; 412*4882a593Smuzhiyun /** 413*4882a593Smuzhiyun * @scale_decrement_interval_low: 414*4882a593Smuzhiyun * PPS25[7:0] - Lower 8 bits of scale decrement interval 415*4882a593Smuzhiyun */ 416*4882a593Smuzhiyun u8 scale_decrement_interval_low; 417*4882a593Smuzhiyun /** 418*4882a593Smuzhiyun * @pps26_reserved: 419*4882a593Smuzhiyun * PPS26[7:0] 420*4882a593Smuzhiyun */ 421*4882a593Smuzhiyun u8 pps26_reserved; 422*4882a593Smuzhiyun /** 423*4882a593Smuzhiyun * @first_line_bpg_offset: 424*4882a593Smuzhiyun * PPS27[4:0] - Number of additional bits that are allocated 425*4882a593Smuzhiyun * for each group on first line of a slice. 426*4882a593Smuzhiyun * PPS27[7:5] - Reserved 427*4882a593Smuzhiyun */ 428*4882a593Smuzhiyun u8 first_line_bpg_offset; 429*4882a593Smuzhiyun /** 430*4882a593Smuzhiyun * @nfl_bpg_offset: 431*4882a593Smuzhiyun * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits 432*4882a593Smuzhiyun * deallocated for each group for groups after the first line of slice. 433*4882a593Smuzhiyun */ 434*4882a593Smuzhiyun __be16 nfl_bpg_offset; 435*4882a593Smuzhiyun /** 436*4882a593Smuzhiyun * @slice_bpg_offset: 437*4882a593Smuzhiyun * PPS30, PPS31[7:0] - Number of bits that are deallocated for each 438*4882a593Smuzhiyun * group to enforce the slice constraint. 439*4882a593Smuzhiyun */ 440*4882a593Smuzhiyun __be16 slice_bpg_offset; 441*4882a593Smuzhiyun /** 442*4882a593Smuzhiyun * @initial_offset: 443*4882a593Smuzhiyun * PPS32,33[7:0] - Initial value for rcXformOffset 444*4882a593Smuzhiyun */ 445*4882a593Smuzhiyun __be16 initial_offset; 446*4882a593Smuzhiyun /** 447*4882a593Smuzhiyun * @final_offset: 448*4882a593Smuzhiyun * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset 449*4882a593Smuzhiyun */ 450*4882a593Smuzhiyun __be16 final_offset; 451*4882a593Smuzhiyun /** 452*4882a593Smuzhiyun * @flatness_min_qp: 453*4882a593Smuzhiyun * PPS36[4:0] - Minimum QP at which flatness is signaled and 454*4882a593Smuzhiyun * flatness QP adjustment is made. 455*4882a593Smuzhiyun * PPS36[7:5] - Reserved 456*4882a593Smuzhiyun */ 457*4882a593Smuzhiyun u8 flatness_min_qp; 458*4882a593Smuzhiyun /** 459*4882a593Smuzhiyun * @flatness_max_qp: 460*4882a593Smuzhiyun * PPS37[4:0] - Max QP at which flatness is signalled and 461*4882a593Smuzhiyun * the flatness adjustment is made. 462*4882a593Smuzhiyun * PPS37[7:5] - Reserved 463*4882a593Smuzhiyun */ 464*4882a593Smuzhiyun u8 flatness_max_qp; 465*4882a593Smuzhiyun /** 466*4882a593Smuzhiyun * @rc_model_size: 467*4882a593Smuzhiyun * PPS38,39[7:0] - Number of bits within RC Model. 468*4882a593Smuzhiyun */ 469*4882a593Smuzhiyun __be16 rc_model_size; 470*4882a593Smuzhiyun /** 471*4882a593Smuzhiyun * @rc_edge_factor: 472*4882a593Smuzhiyun * PPS40[3:0] - Ratio of current activity vs, previous 473*4882a593Smuzhiyun * activity to determine presence of edge. 474*4882a593Smuzhiyun * PPS40[7:4] - Reserved 475*4882a593Smuzhiyun */ 476*4882a593Smuzhiyun u8 rc_edge_factor; 477*4882a593Smuzhiyun /** 478*4882a593Smuzhiyun * @rc_quant_incr_limit0: 479*4882a593Smuzhiyun * PPS41[4:0] - QP threshold used in short term RC 480*4882a593Smuzhiyun * PPS41[7:5] - Reserved 481*4882a593Smuzhiyun */ 482*4882a593Smuzhiyun u8 rc_quant_incr_limit0; 483*4882a593Smuzhiyun /** 484*4882a593Smuzhiyun * @rc_quant_incr_limit1: 485*4882a593Smuzhiyun * PPS42[4:0] - QP threshold used in short term RC 486*4882a593Smuzhiyun * PPS42[7:5] - Reserved 487*4882a593Smuzhiyun */ 488*4882a593Smuzhiyun u8 rc_quant_incr_limit1; 489*4882a593Smuzhiyun /** 490*4882a593Smuzhiyun * @rc_tgt_offset: 491*4882a593Smuzhiyun * PPS43[3:0] - Lower end of the variability range around the target 492*4882a593Smuzhiyun * bits per group that is allowed by short term RC. 493*4882a593Smuzhiyun * PPS43[7:4]- Upper end of the variability range around the target 494*4882a593Smuzhiyun * bits per group that i allowed by short term rc. 495*4882a593Smuzhiyun */ 496*4882a593Smuzhiyun u8 rc_tgt_offset; 497*4882a593Smuzhiyun /** 498*4882a593Smuzhiyun * @rc_buf_thresh: 499*4882a593Smuzhiyun * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for 500*4882a593Smuzhiyun * the 15 ranges defined by 14 thresholds. 501*4882a593Smuzhiyun */ 502*4882a593Smuzhiyun u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1]; 503*4882a593Smuzhiyun /** 504*4882a593Smuzhiyun * @rc_range_parameters: 505*4882a593Smuzhiyun * PPS58[7:0] - PPS87[7:0] 506*4882a593Smuzhiyun * Parameters that correspond to each of the 15 ranges. 507*4882a593Smuzhiyun */ 508*4882a593Smuzhiyun __be16 rc_range_parameters[DSC_NUM_BUF_RANGES]; 509*4882a593Smuzhiyun /** 510*4882a593Smuzhiyun * @native_422_420: 511*4882a593Smuzhiyun * PPS88[0] - 0 = Native 4:2:2 not used 512*4882a593Smuzhiyun * 1 = Native 4:2:2 used 513*4882a593Smuzhiyun * PPS88[1] - 0 = Native 4:2:0 not use 514*4882a593Smuzhiyun * 1 = Native 4:2:0 used 515*4882a593Smuzhiyun * PPS88[7:2] - Reserved 6 bits 516*4882a593Smuzhiyun */ 517*4882a593Smuzhiyun u8 native_422_420; 518*4882a593Smuzhiyun /** 519*4882a593Smuzhiyun * @second_line_bpg_offset: 520*4882a593Smuzhiyun * PPS89[4:0] - Additional bits/group budget for the 521*4882a593Smuzhiyun * second line of a slice in Native 4:2:0 mode. 522*4882a593Smuzhiyun * Set to 0 if DSC minor version is 1 or native420 is 0. 523*4882a593Smuzhiyun * PPS89[7:5] - Reserved 524*4882a593Smuzhiyun */ 525*4882a593Smuzhiyun u8 second_line_bpg_offset; 526*4882a593Smuzhiyun /** 527*4882a593Smuzhiyun * @nsl_bpg_offset: 528*4882a593Smuzhiyun * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated 529*4882a593Smuzhiyun * for each group that is not in the second line of a slice. 530*4882a593Smuzhiyun */ 531*4882a593Smuzhiyun __be16 nsl_bpg_offset; 532*4882a593Smuzhiyun /** 533*4882a593Smuzhiyun * @second_line_offset_adj: 534*4882a593Smuzhiyun * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second 535*4882a593Smuzhiyun * line in Native 4:2:0 mode. 536*4882a593Smuzhiyun */ 537*4882a593Smuzhiyun __be16 second_line_offset_adj; 538*4882a593Smuzhiyun /** 539*4882a593Smuzhiyun * @pps_long_94_reserved: 540*4882a593Smuzhiyun * PPS 94, 95, 96, 97 - Reserved 541*4882a593Smuzhiyun */ 542*4882a593Smuzhiyun u32 pps_long_94_reserved; 543*4882a593Smuzhiyun /** 544*4882a593Smuzhiyun * @pps_long_98_reserved: 545*4882a593Smuzhiyun * PPS 98, 99, 100, 101 - Reserved 546*4882a593Smuzhiyun */ 547*4882a593Smuzhiyun u32 pps_long_98_reserved; 548*4882a593Smuzhiyun /** 549*4882a593Smuzhiyun * @pps_long_102_reserved: 550*4882a593Smuzhiyun * PPS 102, 103, 104, 105 - Reserved 551*4882a593Smuzhiyun */ 552*4882a593Smuzhiyun u32 pps_long_102_reserved; 553*4882a593Smuzhiyun /** 554*4882a593Smuzhiyun * @pps_long_106_reserved: 555*4882a593Smuzhiyun * PPS 106, 107, 108, 109 - reserved 556*4882a593Smuzhiyun */ 557*4882a593Smuzhiyun u32 pps_long_106_reserved; 558*4882a593Smuzhiyun /** 559*4882a593Smuzhiyun * @pps_long_110_reserved: 560*4882a593Smuzhiyun * PPS 110, 111, 112, 113 - reserved 561*4882a593Smuzhiyun */ 562*4882a593Smuzhiyun u32 pps_long_110_reserved; 563*4882a593Smuzhiyun /** 564*4882a593Smuzhiyun * @pps_long_114_reserved: 565*4882a593Smuzhiyun * PPS 114 - 117 - reserved 566*4882a593Smuzhiyun */ 567*4882a593Smuzhiyun u32 pps_long_114_reserved; 568*4882a593Smuzhiyun /** 569*4882a593Smuzhiyun * @pps_long_118_reserved: 570*4882a593Smuzhiyun * PPS 118 - 121 - reserved 571*4882a593Smuzhiyun */ 572*4882a593Smuzhiyun u32 pps_long_118_reserved; 573*4882a593Smuzhiyun /** 574*4882a593Smuzhiyun * @pps_long_122_reserved: 575*4882a593Smuzhiyun * PPS 122- 125 - reserved 576*4882a593Smuzhiyun */ 577*4882a593Smuzhiyun u32 pps_long_122_reserved; 578*4882a593Smuzhiyun /** 579*4882a593Smuzhiyun * @pps_short_126_reserved: 580*4882a593Smuzhiyun * PPS 126, 127 - reserved 581*4882a593Smuzhiyun */ 582*4882a593Smuzhiyun __be16 pps_short_126_reserved; 583*4882a593Smuzhiyun } __packed; 584*4882a593Smuzhiyun 585*4882a593Smuzhiyun /** 586*4882a593Smuzhiyun * struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture Parameter 587*4882a593Smuzhiyun * Set Metadata 588*4882a593Smuzhiyun * 589*4882a593Smuzhiyun * This structure represents the DSC PPS infoframe required to send the Picture 590*4882a593Smuzhiyun * Parameter Set metadata required before enabling VESA Display Stream 591*4882a593Smuzhiyun * Compression. This is based on the DP Secondary Data Packet structure and 592*4882a593Smuzhiyun * comprises of SDP Header as defined &struct dp_sdp_header in drm_dp_helper.h 593*4882a593Smuzhiyun * and PPS payload defined in &struct drm_dsc_picture_parameter_set. 594*4882a593Smuzhiyun * 595*4882a593Smuzhiyun * @pps_header: Header for PPS as per DP SDP header format of type 596*4882a593Smuzhiyun * &struct dp_sdp_header 597*4882a593Smuzhiyun * @pps_payload: PPS payload fields as per DSC specification Table 4-1 598*4882a593Smuzhiyun * as represented in &struct drm_dsc_picture_parameter_set 599*4882a593Smuzhiyun */ 600*4882a593Smuzhiyun struct drm_dsc_pps_infoframe { 601*4882a593Smuzhiyun struct dp_sdp_header pps_header; 602*4882a593Smuzhiyun struct drm_dsc_picture_parameter_set pps_payload; 603*4882a593Smuzhiyun } __packed; 604*4882a593Smuzhiyun 605*4882a593Smuzhiyun void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header); 606*4882a593Smuzhiyun void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, 607*4882a593Smuzhiyun const struct drm_dsc_config *dsc_cfg); 608*4882a593Smuzhiyun int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); 609*4882a593Smuzhiyun 610*4882a593Smuzhiyun #endif /* _DRM_DSC_H_ */ 611