1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * DP83848 ethernet Physical layer 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define DP83848_CTL_REG 0x0 /* Basic Mode Control Reg */ 14*4882a593Smuzhiyun #define DP83848_STAT_REG 0x1 /* Basic Mode Status Reg */ 15*4882a593Smuzhiyun #define DP83848_PHYID1_REG 0x2 /* PHY Idendifier Reg 1 */ 16*4882a593Smuzhiyun #define DP83848_PHYID2_REG 0x3 /* PHY Idendifier Reg 2 */ 17*4882a593Smuzhiyun #define DP83848_ANA_REG 0x4 /* Auto_Neg Advt Reg */ 18*4882a593Smuzhiyun #define DP83848_ANLPA_REG 0x5 /* Auto_neg Link Partner Ability Reg */ 19*4882a593Smuzhiyun #define DP83848_ANE_REG 0x6 /* Auto-neg Expansion Reg */ 20*4882a593Smuzhiyun #define DP83848_PHY_STAT_REG 0x10 /* PHY Status Register */ 21*4882a593Smuzhiyun #define DP83848_PHY_INTR_CTRL_REG 0x11 /* PHY Interrupt Control Register */ 22*4882a593Smuzhiyun #define DP83848_PHY_CTRL_REG 0x19 /* PHY Status Register */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /*--Bit definitions: DP83848_CTL_REG */ 25*4882a593Smuzhiyun #define DP83848_RESET (1 << 15) /* 1= S/W Reset */ 26*4882a593Smuzhiyun #define DP83848_LOOPBACK (1 << 14) /* 1=loopback Enabled */ 27*4882a593Smuzhiyun #define DP83848_SPEED_SELECT (1 << 13) 28*4882a593Smuzhiyun #define DP83848_AUTONEG (1 << 12) 29*4882a593Smuzhiyun #define DP83848_POWER_DOWN (1 << 11) 30*4882a593Smuzhiyun #define DP83848_ISOLATE (1 << 10) 31*4882a593Smuzhiyun #define DP83848_RESTART_AUTONEG (1 << 9) 32*4882a593Smuzhiyun #define DP83848_DUPLEX_MODE (1 << 8) 33*4882a593Smuzhiyun #define DP83848_COLLISION_TEST (1 << 7) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /*--Bit definitions: DP83848_STAT_REG */ 36*4882a593Smuzhiyun #define DP83848_100BASE_T4 (1 << 15) 37*4882a593Smuzhiyun #define DP83848_100BASE_TX_FD (1 << 14) 38*4882a593Smuzhiyun #define DP83848_100BASE_TX_HD (1 << 13) 39*4882a593Smuzhiyun #define DP83848_10BASE_T_FD (1 << 12) 40*4882a593Smuzhiyun #define DP83848_10BASE_T_HD (1 << 11) 41*4882a593Smuzhiyun #define DP83848_MF_PREAMB_SUPPR (1 << 6) 42*4882a593Smuzhiyun #define DP83848_AUTONEG_COMP (1 << 5) 43*4882a593Smuzhiyun #define DP83848_RMT_FAULT (1 << 4) 44*4882a593Smuzhiyun #define DP83848_AUTONEG_ABILITY (1 << 3) 45*4882a593Smuzhiyun #define DP83848_LINK_STATUS (1 << 2) 46*4882a593Smuzhiyun #define DP83848_JABBER_DETECT (1 << 1) 47*4882a593Smuzhiyun #define DP83848_EXTEND_CAPAB (1 << 0) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /*--definitions: DP83848_PHYID1 */ 50*4882a593Smuzhiyun #define DP83848_PHYID1_OUI 0x2000 51*4882a593Smuzhiyun #define DP83848_PHYID2_OUI 0x5c90 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */ 54*4882a593Smuzhiyun #define DP83848_NP (1 << 15) 55*4882a593Smuzhiyun #define DP83848_ACK (1 << 14) 56*4882a593Smuzhiyun #define DP83848_RF (1 << 13) 57*4882a593Smuzhiyun #define DP83848_PAUSE (1 << 10) 58*4882a593Smuzhiyun #define DP83848_T4 (1 << 9) 59*4882a593Smuzhiyun #define DP83848_TX_FDX (1 << 8) 60*4882a593Smuzhiyun #define DP83848_TX_HDX (1 << 7) 61*4882a593Smuzhiyun #define DP83848_10_FDX (1 << 6) 62*4882a593Smuzhiyun #define DP83848_10_HDX (1 << 5) 63*4882a593Smuzhiyun #define DP83848_AN_IEEE_802_3 0x0001 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /*--Bit definitions: DP83848_ANER */ 66*4882a593Smuzhiyun #define DP83848_PDF (1 << 4) 67*4882a593Smuzhiyun #define DP83848_LP_NP_ABLE (1 << 3) 68*4882a593Smuzhiyun #define DP83848_NP_ABLE (1 << 2) 69*4882a593Smuzhiyun #define DP83848_PAGE_RX (1 << 1) 70*4882a593Smuzhiyun #define DP83848_LP_AN_ABLE (1 << 0) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /*--Bit definitions: DP83848_PHY_STAT */ 73*4882a593Smuzhiyun #define DP83848_RX_ERR_LATCH (1 << 13) 74*4882a593Smuzhiyun #define DP83848_POLARITY_STAT (1 << 12) 75*4882a593Smuzhiyun #define DP83848_FALSE_CAR_SENSE (1 << 11) 76*4882a593Smuzhiyun #define DP83848_SIG_DETECT (1 << 10) 77*4882a593Smuzhiyun #define DP83848_DESCRAM_LOCK (1 << 9) 78*4882a593Smuzhiyun #define DP83848_PAGE_RCV (1 << 8) 79*4882a593Smuzhiyun #define DP83848_PHY_RMT_FAULT (1 << 6) 80*4882a593Smuzhiyun #define DP83848_JABBER (1 << 5) 81*4882a593Smuzhiyun #define DP83848_AUTONEG_COMPLETE (1 << 4) 82*4882a593Smuzhiyun #define DP83848_LOOPBACK_STAT (1 << 3) 83*4882a593Smuzhiyun #define DP83848_DUPLEX (1 << 2) 84*4882a593Smuzhiyun #define DP83848_SPEED (1 << 1) 85*4882a593Smuzhiyun #define DP83848_LINK (1 << 0) 86