1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 3*4882a593Smuzhiyun * Copyright (c) 2014 Renesas Electronics Corporation 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __serial_sh_h 9*4882a593Smuzhiyun #define __serial_sh_h 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun enum sh_clk_mode { 12*4882a593Smuzhiyun INT_CLK, 13*4882a593Smuzhiyun EXT_CLK, 14*4882a593Smuzhiyun }; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun enum sh_serial_type { 17*4882a593Smuzhiyun PORT_SCI, 18*4882a593Smuzhiyun PORT_SCIF, 19*4882a593Smuzhiyun PORT_SCIFA, 20*4882a593Smuzhiyun PORT_SCIFB, 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* 24*4882a593Smuzhiyun * Information about SCIF port 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * @base: Register base address 27*4882a593Smuzhiyun * @clk: Input clock rate, used for calculating the baud rate divisor 28*4882a593Smuzhiyun * @clk_mode: Clock mode, set internal (INT) or external (EXT) 29*4882a593Smuzhiyun * @type: Type of SCIF 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun struct sh_serial_platdata { 32*4882a593Smuzhiyun unsigned long base; 33*4882a593Smuzhiyun unsigned int clk; 34*4882a593Smuzhiyun enum sh_clk_mode clk_mode; 35*4882a593Smuzhiyun enum sh_serial_type type; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun #endif /* __serial_sh_h */ 38