1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __SERIAL_PXA_H 8*4882a593Smuzhiyun #define __SERIAL_PXA_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can 12*4882a593Smuzhiyun * easily handle enabling of clock. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun #ifdef CONFIG_CPU_MONAHANS 15*4882a593Smuzhiyun #define UART_CLK_BASE CKENA_21_BTUART 16*4882a593Smuzhiyun #define UART_CLK_REG CKENA 17*4882a593Smuzhiyun #define BTUART_INDEX 0 18*4882a593Smuzhiyun #define FFUART_INDEX 1 19*4882a593Smuzhiyun #define STUART_INDEX 2 20*4882a593Smuzhiyun #elif CONFIG_CPU_PXA25X 21*4882a593Smuzhiyun #define UART_CLK_BASE (1 << 4) /* HWUART */ 22*4882a593Smuzhiyun #define UART_CLK_REG CKEN 23*4882a593Smuzhiyun #define HWUART_INDEX 0 24*4882a593Smuzhiyun #define STUART_INDEX 1 25*4882a593Smuzhiyun #define FFUART_INDEX 2 26*4882a593Smuzhiyun #define BTUART_INDEX 3 27*4882a593Smuzhiyun #else /* PXA27x */ 28*4882a593Smuzhiyun #define UART_CLK_BASE CKEN5_STUART 29*4882a593Smuzhiyun #define UART_CLK_REG CKEN 30*4882a593Smuzhiyun #define STUART_INDEX 0 31*4882a593Smuzhiyun #define FFUART_INDEX 1 32*4882a593Smuzhiyun #define BTUART_INDEX 2 33*4882a593Smuzhiyun #endif 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * Only PXA250 has HWUART, to avoid poluting the code with more macros, 37*4882a593Smuzhiyun * artificially introduce this. 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun #ifndef CONFIG_CPU_PXA25X 40*4882a593Smuzhiyun #define HWUART_INDEX 0xff 41*4882a593Smuzhiyun #endif 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* 44*4882a593Smuzhiyun * struct pxa_serial_platdata - information about a PXA port 45*4882a593Smuzhiyun * 46*4882a593Smuzhiyun * @base: Uart port base register address 47*4882a593Smuzhiyun * @port: Uart port index, for cpu with pinmux for uart / gpio 48*4882a593Smuzhiyun * baudrtatre: Uart port baudrate 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun struct pxa_serial_platdata { 51*4882a593Smuzhiyun struct pxa_uart_regs *base; 52*4882a593Smuzhiyun int port; 53*4882a593Smuzhiyun int baudrate; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #endif /* __SERIAL_PXA_H */ 57