xref: /OK3568_Linux_fs/u-boot/include/dm/platform_data/serial_pl01x.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (c) 2014 Google, Inc
3*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #ifndef __serial_pl01x_h
7*4882a593Smuzhiyun #define __serial_pl01x_h
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun enum pl01x_type {
10*4882a593Smuzhiyun 	TYPE_PL010,
11*4882a593Smuzhiyun 	TYPE_PL011,
12*4882a593Smuzhiyun };
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun /*
15*4882a593Smuzhiyun  *Information about a serial port
16*4882a593Smuzhiyun  *
17*4882a593Smuzhiyun  * @base: Register base address
18*4882a593Smuzhiyun  * @type: Port type
19*4882a593Smuzhiyun  * @clock: Input clock rate, used for calculating the baud rate divisor
20*4882a593Smuzhiyun  * @skip_init: Don't attempt to change port configuration (also means @clock
21*4882a593Smuzhiyun  * is ignored)
22*4882a593Smuzhiyun  */
23*4882a593Smuzhiyun struct pl01x_serial_platdata {
24*4882a593Smuzhiyun 	unsigned long base;
25*4882a593Smuzhiyun 	enum pl01x_type type;
26*4882a593Smuzhiyun 	unsigned int clock;
27*4882a593Smuzhiyun 	bool skip_init;
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #endif
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