1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuration for Xilinx ZynqMP zcu102 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2015 Xilinx, Inc. 5*4882a593Smuzhiyun * Michal Simek <michal.simek@xilinx.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __CONFIG_ZYNQMP_ZCU102_H 11*4882a593Smuzhiyun #define __CONFIG_ZYNQMP_ZCU102_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define CONFIG_ZYNQ_SDHCI1 14*4882a593Smuzhiyun #define CONFIG_ZYNQ_I2C0 15*4882a593Smuzhiyun #define CONFIG_ZYNQ_I2C1 16*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MAX_HOPS 1 17*4882a593Smuzhiyun #define CONFIG_SYS_NUM_I2C_BUSES 18 18*4882a593Smuzhiyun #define CONFIG_SYS_I2C_BUSES { \ 19*4882a593Smuzhiyun {0, {I2C_NULL_HOP} }, \ 20*4882a593Smuzhiyun {0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \ 21*4882a593Smuzhiyun {0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \ 22*4882a593Smuzhiyun {0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \ 23*4882a593Smuzhiyun {1, {I2C_NULL_HOP} }, \ 24*4882a593Smuzhiyun {1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \ 25*4882a593Smuzhiyun {1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \ 26*4882a593Smuzhiyun {1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \ 27*4882a593Smuzhiyun {1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \ 28*4882a593Smuzhiyun {1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \ 29*4882a593Smuzhiyun {1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \ 30*4882a593Smuzhiyun {1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \ 31*4882a593Smuzhiyun {1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \ 32*4882a593Smuzhiyun {1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \ 33*4882a593Smuzhiyun {1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \ 34*4882a593Smuzhiyun {1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \ 35*4882a593Smuzhiyun {1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \ 36*4882a593Smuzhiyun {1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \ 37*4882a593Smuzhiyun } 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define CONFIG_SYS_I2C_ZYNQ 40*4882a593Smuzhiyun #define CONFIG_PCA953X 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 45*4882a593Smuzhiyun #define CONFIG_ZYNQ_EEPROM_BUS 5 46*4882a593Smuzhiyun #define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54 47*4882a593Smuzhiyun #define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0x20 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #include <configs/xilinx_zynqmp.h> 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #endif /* __CONFIG_ZYNQMP_ZCU102_H */ 52