1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuration for Xilinx ZynqMP zc1751 XM019 DC5 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2015 Xilinx, Inc. 5*4882a593Smuzhiyun * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> 6*4882a593Smuzhiyun * Michal Simek <michal.simek@xilinx.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H 12*4882a593Smuzhiyun #define __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define CONFIG_ZYNQ_SDHCI0 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #include <configs/xilinx_zynqmp.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #endif /* __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H */ 19