1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuration for Xilinx ZynqMP zc1751 XM015 DC1 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2015 Xilinx, Inc. 5*4882a593Smuzhiyun * Michal Simek <michal.simek@xilinx.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H 11*4882a593Smuzhiyun #define __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define CONFIG_ZYNQ_SDHCI0 14*4882a593Smuzhiyun #define CONFIG_ZYNQ_SDHCI1 15*4882a593Smuzhiyun #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include <configs/xilinx_zynqmp.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #endif /* __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H */ 20