1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuration for Xilinx ZynqMP emulation platforms 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2014 - 2015 Xilinx, Inc. 5*4882a593Smuzhiyun * Michal Simek <michal.simek@xilinx.com> 6*4882a593Smuzhiyun * Siva Durga Prasad Paladugu <sivadur@xilinx.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Based on Configuration for Versatile Express 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef __CONFIG_ZYNQMP_EP_H 14*4882a593Smuzhiyun #define __CONFIG_ZYNQMP_EP_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000 17*4882a593Smuzhiyun #define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ >> 9) 18*4882a593Smuzhiyun #define CONFIG_ZYNQ_EEPROM 19*4882a593Smuzhiyun #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ 20*4882a593Smuzhiyun ZYNQMP_USB1_XHCI_BASEADDR} 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define COUNTER_FREQUENCY 4000000 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #include <configs/xilinx_zynqmp.h> 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #endif /* __CONFIG_ZYNQMP_EP_H */ 27