1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * WORK Microwave work_92105 board configuration file 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2014 DENX Software Engineering GmbH 5*4882a593Smuzhiyun * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __CONFIG_WORK_92105_H__ 11*4882a593Smuzhiyun #define __CONFIG_WORK_92105_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* SoC and board defines */ 14*4882a593Smuzhiyun #include <linux/sizes.h> 15*4882a593Smuzhiyun #include <asm/arch/cpu.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * Define work_92105 machine type by hand -- done only for compatibility 19*4882a593Smuzhiyun * with original board code 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun #define CONFIG_MACH_TYPE 736 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define CONFIG_SYS_ICACHE_OFF 24*4882a593Smuzhiyun #define CONFIG_SYS_DCACHE_OFF 25*4882a593Smuzhiyun #if !defined(CONFIG_SPL_BUILD) 26*4882a593Smuzhiyun #define CONFIG_SKIP_LOWLEVEL_INIT 27*4882a593Smuzhiyun #endif 28*4882a593Smuzhiyun #define CONFIG_BOARD_EARLY_INIT_R 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* generate LPC32XX-specific SPL image */ 31*4882a593Smuzhiyun #define CONFIG_LPC32XX_SPL 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * Memory configurations 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 37*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN SZ_1M 38*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE 39*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE SZ_128M 40*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x80100000 41*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K) 42*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \ 47*4882a593Smuzhiyun - GENERATED_GBL_DATA_SIZE) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* 50*4882a593Smuzhiyun * Serial Driver 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun #define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* 55*4882a593Smuzhiyun * Ethernet Driver 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define CONFIG_PHY_SMSC 59*4882a593Smuzhiyun #define CONFIG_LPC32XX_ETH 60*4882a593Smuzhiyun #define CONFIG_PHY_ADDR 0 61*4882a593Smuzhiyun #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 62*4882a593Smuzhiyun /* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* 65*4882a593Smuzhiyun * I2C driver 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define CONFIG_SYS_I2C_LPC32XX 69*4882a593Smuzhiyun #define CONFIG_SYS_I2C 70*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SPEED 350000 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* 73*4882a593Smuzhiyun * I2C EEPROM 74*4882a593Smuzhiyun */ 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 77*4882a593Smuzhiyun #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* 80*4882a593Smuzhiyun * I2C RTC 81*4882a593Smuzhiyun */ 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define CONFIG_RTC_DS1374 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* 86*4882a593Smuzhiyun * U-Boot General Configurations 87*4882a593Smuzhiyun */ 88*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 89*4882a593Smuzhiyun #define CONFIG_SYS_CBSIZE 1024 90*4882a593Smuzhiyun #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define CONFIG_AUTO_COMPLETE 93*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* 96*4882a593Smuzhiyun * NAND chip timings for FIXME: which one? 97*4882a593Smuzhiyun */ 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 100*4882a593Smuzhiyun #define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 101*4882a593Smuzhiyun #define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818 102*4882a593Smuzhiyun #define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000 103*4882a593Smuzhiyun #define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545 104*4882a593Smuzhiyun #define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000 105*4882a593Smuzhiyun #define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* 108*4882a593Smuzhiyun * NAND 109*4882a593Smuzhiyun */ 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* driver configuration */ 112*4882a593Smuzhiyun #define CONFIG_SYS_NAND_SELF_INIT 113*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE 1 114*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_CHIPS 1 115*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BASE MLC_NAND_BASE 116*4882a593Smuzhiyun #define CONFIG_NAND_LPC32XX_MLC 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* 119*4882a593Smuzhiyun * GPIO 120*4882a593Smuzhiyun */ 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #define CONFIG_LPC32XX_GPIO 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* 125*4882a593Smuzhiyun * SSP/SPI/DISPLAY 126*4882a593Smuzhiyun */ 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #define CONFIG_LPC32XX_SSP_TIMEOUT 100000 129*4882a593Smuzhiyun /* 130*4882a593Smuzhiyun * Environment 131*4882a593Smuzhiyun */ 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #define CONFIG_ENV_SIZE 0x00020000 134*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET 0x00100000 135*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET_REDUND 0x00120000 136*4882a593Smuzhiyun #define CONFIG_ENV_ADDR 0x80000100 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* 139*4882a593Smuzhiyun * Boot Linux 140*4882a593Smuzhiyun */ 141*4882a593Smuzhiyun #define CONFIG_CMDLINE_TAG 142*4882a593Smuzhiyun #define CONFIG_SETUP_MEMORY_TAGS 143*4882a593Smuzhiyun #define CONFIG_INITRD_TAG 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #define CONFIG_BOOTFILE "uImage" 146*4882a593Smuzhiyun #define CONFIG_LOADADDR 0x80008000 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* 149*4882a593Smuzhiyun * SPL 150*4882a593Smuzhiyun */ 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun /* SPL will be executed at offset 0 */ 153*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE 0x00000000 154*4882a593Smuzhiyun /* SPL will use SRAM as stack */ 155*4882a593Smuzhiyun #define CONFIG_SPL_STACK 0x0000FFF8 156*4882a593Smuzhiyun /* Use the framework and generic lib */ 157*4882a593Smuzhiyun #define CONFIG_SPL_FRAMEWORK 158*4882a593Smuzhiyun /* SPL will use serial */ 159*4882a593Smuzhiyun /* SPL will load U-Boot from NAND offset 0x40000 */ 160*4882a593Smuzhiyun #define CONFIG_SPL_NAND_DRIVERS 161*4882a593Smuzhiyun #define CONFIG_SPL_NAND_BASE 162*4882a593Smuzhiyun #define CONFIG_SPL_NAND_BOOT 163*4882a593Smuzhiyun #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000 164*4882a593Smuzhiyun #define CONFIG_SPL_PAD_TO 0x20000 165*4882a593Smuzhiyun /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ 166*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */ 167*4882a593Smuzhiyun #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 168*4882a593Smuzhiyun #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun /* 171*4882a593Smuzhiyun * Include SoC specific configuration 172*4882a593Smuzhiyun */ 173*4882a593Smuzhiyun #include <asm/arch/config.h> 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun #endif /* __CONFIG_WORK_92105_H__*/ 176