1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Configuation settings for the WB50N CPU Module. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __CONFIG_H 7*4882a593Smuzhiyun #define __CONFIG_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <asm/hardware.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* ARM asynchronous clock */ 12*4882a593Smuzhiyun #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 13*4882a593Smuzhiyun #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CONFIG_ARCH_CPU_INIT 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 18*4882a593Smuzhiyun #define CONFIG_SETUP_MEMORY_TAGS 19*4882a593Smuzhiyun #define CONFIG_INITRD_TAG 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #ifndef CONFIG_SPL_BUILD 22*4882a593Smuzhiyun #define CONFIG_SKIP_LOWLEVEL_INIT 23*4882a593Smuzhiyun #endif 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* general purpose I/O */ 26*4882a593Smuzhiyun #define CONFIG_AT91_GPIO 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* serial console */ 29*4882a593Smuzhiyun #define CONFIG_ATMEL_USART 30*4882a593Smuzhiyun #define CONFIG_USART_BASE ATMEL_BASE_DBGU 31*4882a593Smuzhiyun #define CONFIG_USART_ID ATMEL_ID_DBGU 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * BOOTP options 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun #define CONFIG_BOOTP_BOOTFILESIZE 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* SDRAM */ 39*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 40*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS 41*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE 0x04000000 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD 44*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0x310000 45*4882a593Smuzhiyun #else 46*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR \ 47*4882a593Smuzhiyun (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) 48*4882a593Smuzhiyun #endif 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START 0x21000000 51*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END 0x22000000 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* NAND flash */ 54*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE 1 55*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 56*4882a593Smuzhiyun /* our ALE is AD21 */ 57*4882a593Smuzhiyun #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 58*4882a593Smuzhiyun /* our CLE is AD22 */ 59*4882a593Smuzhiyun #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 60*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ONFI_DETECTION 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* Ethernet Hardware */ 63*4882a593Smuzhiyun #define CONFIG_MACB 64*4882a593Smuzhiyun #define CONFIG_RMII 65*4882a593Smuzhiyun #define CONFIG_NET_RETRY_COUNT 20 66*4882a593Smuzhiyun #define CONFIG_MACB_SEARCH_PHY 67*4882a593Smuzhiyun #define CONFIG_RGMII 68*4882a593Smuzhiyun #define CONFIG_ETHADDR C0:EE:40:00:00:00 69*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 1 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 74*4882a593Smuzhiyun "autoload=no\0" \ 75*4882a593Smuzhiyun "autostart=no\0" 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* bootstrap + u-boot + env in nandflash */ 78*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET 0xA0000 79*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET_REDUND 0xC0000 80*4882a593Smuzhiyun #define CONFIG_ENV_SIZE 0x20000 81*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND \ 82*4882a593Smuzhiyun "nand read 0x22000000 0x000e0000 0x500000; " \ 83*4882a593Smuzhiyun "bootm" 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define CONFIG_BOOTARGS \ 86*4882a593Smuzhiyun "rw rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs" 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #define CONFIG_BAUDRATE 115200 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define CONFIG_SYS_CBSIZE 1024 91*4882a593Smuzhiyun #define CONFIG_SYS_MAXARGS 16 92*4882a593Smuzhiyun #define CONFIG_SYS_PBSIZE \ 93*4882a593Smuzhiyun (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* Size of malloc() pool */ 96*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* SPL */ 99*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE 0x300000 100*4882a593Smuzhiyun #define CONFIG_SPL_MAX_SIZE 0x10000 101*4882a593Smuzhiyun #define CONFIG_SPL_BSS_START_ADDR 0x20000000 102*4882a593Smuzhiyun #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 103*4882a593Smuzhiyun #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 104*4882a593Smuzhiyun #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (512 << 10) 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define CONFIG_SPL_NAND_DRIVERS 109*4882a593Smuzhiyun #define CONFIG_SPL_NAND_BASE 110*4882a593Smuzhiyun #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 111*4882a593Smuzhiyun #define CONFIG_SYS_NAND_5_ADDR_CYCLE 112*4882a593Smuzhiyun #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 113*4882a593Smuzhiyun #define CONFIG_SYS_NAND_PAGE_COUNT 64 114*4882a593Smuzhiyun #define CONFIG_SYS_NAND_OOBSIZE 64 115*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 116*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #endif 119