xref: /OK3568_Linux_fs/u-boot/include/configs/warp7.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (C) 2016 NXP Semiconductors
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Configuration settings for the i.MX7S Warp board.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #ifndef __WARP7_CONFIG_H
10*4882a593Smuzhiyun #define __WARP7_CONFIG_H
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include "mx7_common.h"
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #define PHYS_SDRAM_SIZE			SZ_512M
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #define CONFIG_MXC_UART_BASE		UART1_IPS_BASE_ADDR
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun /* Size of malloc() pool */
19*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN		(35 * SZ_1M)
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun /* MMC Config*/
22*4882a593Smuzhiyun #define CONFIG_SYS_FSL_ESDHC_ADDR       USDHC3_BASE_ADDR
23*4882a593Smuzhiyun #define CONFIG_SUPPORT_EMMC_BOOT
24*4882a593Smuzhiyun #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
25*4882a593Smuzhiyun #define CONFIG_SYS_MMC_IMG_LOAD_PART	1
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define CONFIG_DFU_ENV_SETTINGS \
28*4882a593Smuzhiyun 	"dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \
31*4882a593Smuzhiyun 	CONFIG_DFU_ENV_SETTINGS \
32*4882a593Smuzhiyun 	"script=boot.scr\0" \
33*4882a593Smuzhiyun 	"image=zImage\0" \
34*4882a593Smuzhiyun 	"console=ttymxc0\0" \
35*4882a593Smuzhiyun 	"ethact=usb_ether\0" \
36*4882a593Smuzhiyun 	"fdt_high=0xffffffff\0" \
37*4882a593Smuzhiyun 	"initrd_high=0xffffffff\0" \
38*4882a593Smuzhiyun 	"fdt_file=imx7s-warp.dtb\0" \
39*4882a593Smuzhiyun 	"fdt_addr=0x83000000\0" \
40*4882a593Smuzhiyun 	"boot_fdt=try\0" \
41*4882a593Smuzhiyun 	"ip_dyn=yes\0" \
42*4882a593Smuzhiyun 	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
43*4882a593Smuzhiyun 	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
44*4882a593Smuzhiyun 	"finduuid=part uuid mmc 0:2 uuid\0" \
45*4882a593Smuzhiyun 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
46*4882a593Smuzhiyun 		"root=PARTUUID=${uuid} rootwait rw\0" \
47*4882a593Smuzhiyun 	"loadbootscript=" \
48*4882a593Smuzhiyun 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
49*4882a593Smuzhiyun 	"bootscript=echo Running bootscript from mmc ...; " \
50*4882a593Smuzhiyun 		"source\0" \
51*4882a593Smuzhiyun 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
52*4882a593Smuzhiyun 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
53*4882a593Smuzhiyun 	"mmcboot=echo Booting from mmc ...; " \
54*4882a593Smuzhiyun 		"run finduuid; " \
55*4882a593Smuzhiyun 		"run mmcargs; " \
56*4882a593Smuzhiyun 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
57*4882a593Smuzhiyun 			"if run loadfdt; then " \
58*4882a593Smuzhiyun 				"bootz ${loadaddr} - ${fdt_addr}; " \
59*4882a593Smuzhiyun 			"else " \
60*4882a593Smuzhiyun 				"if test ${boot_fdt} = try; then " \
61*4882a593Smuzhiyun 					"bootz; " \
62*4882a593Smuzhiyun 				"else " \
63*4882a593Smuzhiyun 					"echo WARN: Cannot load the DT; " \
64*4882a593Smuzhiyun 				"fi; " \
65*4882a593Smuzhiyun 			"fi; " \
66*4882a593Smuzhiyun 		"else " \
67*4882a593Smuzhiyun 			"bootz; " \
68*4882a593Smuzhiyun 		"fi;\0" \
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND \
71*4882a593Smuzhiyun 	   "mmc dev ${mmcdev};" \
72*4882a593Smuzhiyun 	   "mmc dev ${mmcdev}; if mmc rescan; then " \
73*4882a593Smuzhiyun 		   "if run loadbootscript; then " \
74*4882a593Smuzhiyun 			   "run bootscript; " \
75*4882a593Smuzhiyun 		   "else " \
76*4882a593Smuzhiyun 			   "if run loadimage; then " \
77*4882a593Smuzhiyun 				   "run mmcboot; " \
78*4882a593Smuzhiyun 			   "fi; " \
79*4882a593Smuzhiyun 		   "fi; " \
80*4882a593Smuzhiyun 	   "fi"
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START	0x80000000
83*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x20000000)
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
86*4882a593Smuzhiyun #define CONFIG_SYS_HZ			1000
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun /* Physical Memory Map */
89*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS		1
90*4882a593Smuzhiyun #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
93*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
94*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_OFFSET \
97*4882a593Smuzhiyun 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
98*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR \
99*4882a593Smuzhiyun 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun /* I2C configs */
102*4882a593Smuzhiyun #define CONFIG_SYS_I2C
103*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC
104*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC_I2C1
105*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SPEED		100000
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun /* PMIC */
108*4882a593Smuzhiyun #define CONFIG_POWER
109*4882a593Smuzhiyun #define CONFIG_POWER_I2C
110*4882a593Smuzhiyun #define CONFIG_POWER_PFUZE3000
111*4882a593Smuzhiyun #define CONFIG_POWER_PFUZE3000_I2C_ADDR	0x08
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun /* environment organization */
114*4882a593Smuzhiyun #define CONFIG_ENV_SIZE			SZ_8K
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET		(8 * SZ_64K)
117*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USDHC_NUM	1
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun #define CONFIG_SYS_MMC_ENV_DEV		0
120*4882a593Smuzhiyun #define CONFIG_SYS_MMC_ENV_PART		0
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun /* USB Configs */
123*4882a593Smuzhiyun #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
126*4882a593Smuzhiyun #define CONFIG_MXC_USB_FLAGS		0
127*4882a593Smuzhiyun #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG1 port enabled */
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun #define CONFIG_IMX_THERMAL
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun #define CONFIG_USBD_HS
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun #define CONFIG_USB_FUNCTION_MASS_STORAGE
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun /* USB Device Firmware Update support */
136*4882a593Smuzhiyun #define CONFIG_SYS_DFU_DATA_BUF_SIZE	SZ_16M
137*4882a593Smuzhiyun #define DFU_DEFAULT_POLL_TIMEOUT	300
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun #define CONFIG_USBNET_DEV_ADDR		"de:ad:be:af:00:01"
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun #endif
142