1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuration for Versatile Express. Parts were derived from other ARM 3*4882a593Smuzhiyun * configurations. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __VEXPRESS_AEMV8A_H 9*4882a593Smuzhiyun #define __VEXPRESS_AEMV8A_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP 12*4882a593Smuzhiyun #ifndef CONFIG_SEMIHOSTING 13*4882a593Smuzhiyun #error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING 14*4882a593Smuzhiyun #endif 15*4882a593Smuzhiyun #define CONFIG_ARMV8_SWITCH_TO_EL1 16*4882a593Smuzhiyun #endif 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CONFIG_REMAKE_ELF 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define CONFIG_SUPPORT_RAW_INITRD 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Link Definitions */ 23*4882a593Smuzhiyun #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ 24*4882a593Smuzhiyun defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) 25*4882a593Smuzhiyun /* ATF loads u-boot here for BASE_FVP model */ 26*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x88000000 27*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) 28*4882a593Smuzhiyun #elif CONFIG_TARGET_VEXPRESS64_JUNO 29*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0xe0000000 30*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 31*4882a593Smuzhiyun #endif 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* CS register bases for the original memory map. */ 36*4882a593Smuzhiyun #define V2M_PA_CS0 0x00000000 37*4882a593Smuzhiyun #define V2M_PA_CS1 0x14000000 38*4882a593Smuzhiyun #define V2M_PA_CS2 0x18000000 39*4882a593Smuzhiyun #define V2M_PA_CS3 0x1c000000 40*4882a593Smuzhiyun #define V2M_PA_CS4 0x0c000000 41*4882a593Smuzhiyun #define V2M_PA_CS5 0x10000000 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define V2M_PERIPH_OFFSET(x) (x << 16) 44*4882a593Smuzhiyun #define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1)) 45*4882a593Smuzhiyun #define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2)) 46*4882a593Smuzhiyun #define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3)) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define V2M_BASE 0x80000000 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* Common peripherals relative to CS7. */ 51*4882a593Smuzhiyun #define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) 52*4882a593Smuzhiyun #define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) 53*4882a593Smuzhiyun #define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6)) 54*4882a593Smuzhiyun #define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7)) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 57*4882a593Smuzhiyun #define V2M_UART0 0x7ff80000 58*4882a593Smuzhiyun #define V2M_UART1 0x7ff70000 59*4882a593Smuzhiyun #else /* Not Juno */ 60*4882a593Smuzhiyun #define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9)) 61*4882a593Smuzhiyun #define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10)) 62*4882a593Smuzhiyun #define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11)) 63*4882a593Smuzhiyun #define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12)) 64*4882a593Smuzhiyun #endif 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15)) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17)) 69*4882a593Smuzhiyun #define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18)) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22)) 72*4882a593Smuzhiyun #define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23)) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26)) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31)) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* System register offsets. */ 79*4882a593Smuzhiyun #define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) 80*4882a593Smuzhiyun #define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) 81*4882a593Smuzhiyun #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* Generic Timer Definitions */ 84*4882a593Smuzhiyun #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* Generic Interrupt Controller Definitions */ 87*4882a593Smuzhiyun #ifdef CONFIG_GICV3 88*4882a593Smuzhiyun #define GICD_BASE (0x2f000000) 89*4882a593Smuzhiyun #define GICR_BASE (0x2f100000) 90*4882a593Smuzhiyun #else 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ 93*4882a593Smuzhiyun defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) 94*4882a593Smuzhiyun #define GICD_BASE (0x2f000000) 95*4882a593Smuzhiyun #define GICC_BASE (0x2c000000) 96*4882a593Smuzhiyun #elif CONFIG_TARGET_VEXPRESS64_JUNO 97*4882a593Smuzhiyun #define GICD_BASE (0x2C010000) 98*4882a593Smuzhiyun #define GICC_BASE (0x2C02f000) 99*4882a593Smuzhiyun #endif 100*4882a593Smuzhiyun #endif /* !CONFIG_GICV3 */ 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* Size of malloc() pool */ 103*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* Ethernet Configuration */ 106*4882a593Smuzhiyun #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 107*4882a593Smuzhiyun /* The real hardware Versatile express uses SMSC9118 */ 108*4882a593Smuzhiyun #define CONFIG_SMC911X 1 109*4882a593Smuzhiyun #define CONFIG_SMC911X_32_BIT 1 110*4882a593Smuzhiyun #define CONFIG_SMC911X_BASE (0x018000000) 111*4882a593Smuzhiyun #else 112*4882a593Smuzhiyun /* The Vexpress64 simulators use SMSC91C111 */ 113*4882a593Smuzhiyun #define CONFIG_SMC91111 1 114*4882a593Smuzhiyun #define CONFIG_SMC91111_BASE (0x01A000000) 115*4882a593Smuzhiyun #endif 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* PL011 Serial Configuration */ 118*4882a593Smuzhiyun #define CONFIG_CONS_INDEX 0 119*4882a593Smuzhiyun #define CONFIG_PL01X_SERIAL 120*4882a593Smuzhiyun #define CONFIG_PL011_SERIAL 121*4882a593Smuzhiyun #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 122*4882a593Smuzhiyun #define CONFIG_PL011_CLOCK 7273800 123*4882a593Smuzhiyun #else 124*4882a593Smuzhiyun #define CONFIG_PL011_CLOCK 24000000 125*4882a593Smuzhiyun #endif 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /*#define CONFIG_MENU_SHOW*/ 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /* BOOTP options */ 130*4882a593Smuzhiyun #define CONFIG_BOOTP_BOOTFILESIZE 131*4882a593Smuzhiyun #define CONFIG_BOOTP_BOOTPATH 132*4882a593Smuzhiyun #define CONFIG_BOOTP_GATEWAY 133*4882a593Smuzhiyun #define CONFIG_BOOTP_HOSTNAME 134*4882a593Smuzhiyun #define CONFIG_BOOTP_PXE 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* Miscellaneous configurable options */ 137*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* Physical Memory Map */ 140*4882a593Smuzhiyun #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ 141*4882a593Smuzhiyun /* Top 16MB reserved for secure world use */ 142*4882a593Smuzhiyun #define DRAM_SEC_SIZE 0x01000000 143*4882a593Smuzhiyun #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE 144*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 147*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 2 148*4882a593Smuzhiyun #define PHYS_SDRAM_2 (0x880000000) 149*4882a593Smuzhiyun #define PHYS_SDRAM_2_SIZE 0x180000000 150*4882a593Smuzhiyun #else 151*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 152*4882a593Smuzhiyun #endif 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* Enable memtest */ 155*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 156*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun /* Initial environment variables */ 159*4882a593Smuzhiyun #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 160*4882a593Smuzhiyun /* 161*4882a593Smuzhiyun * Defines where the kernel and FDT exist in NOR flash and where it will 162*4882a593Smuzhiyun * be copied into DRAM 163*4882a593Smuzhiyun */ 164*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 165*4882a593Smuzhiyun "kernel_name=norkern\0" \ 166*4882a593Smuzhiyun "kernel_alt_name=Image\0" \ 167*4882a593Smuzhiyun "kernel_addr=0x80080000\0" \ 168*4882a593Smuzhiyun "initrd_name=ramdisk.img\0" \ 169*4882a593Smuzhiyun "initrd_addr=0x84000000\0" \ 170*4882a593Smuzhiyun "fdtfile=board.dtb\0" \ 171*4882a593Smuzhiyun "fdt_alt_name=juno\0" \ 172*4882a593Smuzhiyun "fdt_addr=0x83000000\0" \ 173*4882a593Smuzhiyun "fdt_high=0xffffffffffffffff\0" \ 174*4882a593Smuzhiyun "initrd_high=0xffffffffffffffff\0" \ 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* Copy the kernel and FDT to DRAM memory and boot */ 177*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr} ; " \ 178*4882a593Smuzhiyun "if test $? -eq 1; then "\ 179*4882a593Smuzhiyun " echo Loading ${kernel_alt_name} instead of "\ 180*4882a593Smuzhiyun "${kernel_name}; "\ 181*4882a593Smuzhiyun " afs load ${kernel_alt_name} ${kernel_addr};"\ 182*4882a593Smuzhiyun "fi ; "\ 183*4882a593Smuzhiyun "afs load ${fdtfile} ${fdt_addr} ; " \ 184*4882a593Smuzhiyun "if test $? -eq 1; then "\ 185*4882a593Smuzhiyun " echo Loading ${fdt_alt_name} instead of "\ 186*4882a593Smuzhiyun "${fdtfile}; "\ 187*4882a593Smuzhiyun " afs load ${fdt_alt_name} ${fdt_addr}; "\ 188*4882a593Smuzhiyun "fi ; "\ 189*4882a593Smuzhiyun "fdt addr ${fdt_addr}; fdt resize; " \ 190*4882a593Smuzhiyun "if afs load ${initrd_name} ${initrd_addr} ; "\ 191*4882a593Smuzhiyun "then "\ 192*4882a593Smuzhiyun " setenv initrd_param ${initrd_addr}; "\ 193*4882a593Smuzhiyun " else setenv initrd_param -; "\ 194*4882a593Smuzhiyun "fi ; " \ 195*4882a593Smuzhiyun "booti ${kernel_addr} ${initrd_param} ${fdt_addr}" 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP 199*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 200*4882a593Smuzhiyun "kernel_name=Image\0" \ 201*4882a593Smuzhiyun "kernel_addr=0x80080000\0" \ 202*4882a593Smuzhiyun "initrd_name=ramdisk.img\0" \ 203*4882a593Smuzhiyun "initrd_addr=0x88000000\0" \ 204*4882a593Smuzhiyun "fdtfile=devtree.dtb\0" \ 205*4882a593Smuzhiyun "fdt_addr=0x83000000\0" \ 206*4882a593Smuzhiyun "fdt_high=0xffffffffffffffff\0" \ 207*4882a593Smuzhiyun "initrd_high=0xffffffffffffffff\0" 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND "smhload ${kernel_name} ${kernel_addr}; " \ 210*4882a593Smuzhiyun "smhload ${fdtfile} ${fdt_addr}; " \ 211*4882a593Smuzhiyun "smhload ${initrd_name} ${initrd_addr} "\ 212*4882a593Smuzhiyun "initrd_end; " \ 213*4882a593Smuzhiyun "fdt addr ${fdt_addr}; fdt resize; " \ 214*4882a593Smuzhiyun "fdt chosen ${initrd_addr} ${initrd_end}; " \ 215*4882a593Smuzhiyun "booti $kernel_addr - $fdt_addr" 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM 219*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 220*4882a593Smuzhiyun "kernel_addr=0x80080000\0" \ 221*4882a593Smuzhiyun "initrd_addr=0x84000000\0" \ 222*4882a593Smuzhiyun "fdt_addr=0x83000000\0" \ 223*4882a593Smuzhiyun "fdt_high=0xffffffffffffffff\0" \ 224*4882a593Smuzhiyun "initrd_high=0xffffffffffffffff\0" 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND "booti $kernel_addr $initrd_addr $fdt_addr" 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun #endif 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun /* Monitor Command Prompt */ 232*4882a593Smuzhiyun #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 233*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 234*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 235*4882a593Smuzhiyun #define CONFIG_SYS_MAXARGS 64 /* max command args */ 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 238*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE 0x08000000 239*4882a593Smuzhiyun /* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */ 240*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT 259 241*4882a593Smuzhiyun /* Store environment at top of flash in the same location as blank.img */ 242*4882a593Smuzhiyun /* in the Juno firmware. */ 243*4882a593Smuzhiyun #define CONFIG_ENV_ADDR 0x0BFC0000 244*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE 0x00010000 245*4882a593Smuzhiyun #else 246*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE 0x0C000000 247*4882a593Smuzhiyun /* 256 x 256KiB sectors */ 248*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT 256 249*4882a593Smuzhiyun /* Store environment at top of flash */ 250*4882a593Smuzhiyun #define CONFIG_ENV_ADDR 0x0FFC0000 251*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE 0x00040000 252*4882a593Smuzhiyun #endif 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI 1 255*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER 1 256*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 257*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS 1 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ 260*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ 261*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ 262*4882a593Smuzhiyun #define FLASH_MAX_SECTOR_SIZE 0x00040000 263*4882a593Smuzhiyun #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun #endif /* __VEXPRESS_AEMV8A_H */ 266