1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * include/configs/ulcb.h 3*4882a593Smuzhiyun * This file is ULCB board configuration. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2017 Renesas Electronics Corporation 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __ULCB_H 11*4882a593Smuzhiyun #define __ULCB_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #undef DEBUG 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CONFIG_RCAR_BOARD_STRING "ULCB" 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include "rcar-gen3-common.h" 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* M3 ULCB has 2 banks, each with 1 GiB of RAM */ 20*4882a593Smuzhiyun #if defined(CONFIG_R8A7796) 21*4882a593Smuzhiyun #undef PHYS_SDRAM_1_SIZE 22*4882a593Smuzhiyun #undef PHYS_SDRAM_2_SIZE 23*4882a593Smuzhiyun #define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE) 24*4882a593Smuzhiyun #define PHYS_SDRAM_2_SIZE 0x40000000u 25*4882a593Smuzhiyun #endif 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* SCIF */ 28*4882a593Smuzhiyun #define CONFIG_CONS_SCIF2 29*4882a593Smuzhiyun #define CONFIG_CONS_INDEX 2 30*4882a593Smuzhiyun #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* [A] Hyper Flash */ 33*4882a593Smuzhiyun /* use to RPC(SPI Multi I/O Bus Controller) */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Ethernet RAVB */ 36*4882a593Smuzhiyun #define CONFIG_NET_MULTI 37*4882a593Smuzhiyun #define CONFIG_PHY_MICREL 38*4882a593Smuzhiyun #define CONFIG_BITBANGMII 39*4882a593Smuzhiyun #define CONFIG_BITBANGMII_MULTI 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Board Clock */ 42*4882a593Smuzhiyun /* XTAL_CLK : 33.33MHz */ 43*4882a593Smuzhiyun #define RCAR_XTAL_CLK 33333333u 44*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK 45*4882a593Smuzhiyun /* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */ 46*4882a593Smuzhiyun /* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */ 47*4882a593Smuzhiyun #define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) 48*4882a593Smuzhiyun #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2) 49*4882a593Smuzhiyun #define CONFIG_S3D2_CLK_FREQ (266666666u/2) 50*4882a593Smuzhiyun #define CONFIG_S3D4_CLK_FREQ (266666666u/4) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* Generic Timer Definitions (use in assembler source) */ 53*4882a593Smuzhiyun #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* Generic Interrupt Controller Definitions */ 56*4882a593Smuzhiyun #define CONFIG_GICV2 57*4882a593Smuzhiyun #define GICD_BASE 0xF1010000 58*4882a593Smuzhiyun #define GICC_BASE 0xF1020000 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* CPLD SPI */ 61*4882a593Smuzhiyun #define CONFIG_CMD_SPI 62*4882a593Smuzhiyun #define CONFIG_SOFT_SPI 63*4882a593Smuzhiyun #define SPI_DELAY udelay(0) 64*4882a593Smuzhiyun #define SPI_SDA(val) ulcb_softspi_sda(val) 65*4882a593Smuzhiyun #define SPI_SCL(val) ulcb_softspi_scl(val) 66*4882a593Smuzhiyun #define SPI_READ ulcb_softspi_read() 67*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 68*4882a593Smuzhiyun void ulcb_softspi_sda(int); 69*4882a593Smuzhiyun void ulcb_softspi_scl(int); 70*4882a593Smuzhiyun unsigned char ulcb_softspi_read(void); 71*4882a593Smuzhiyun #endif 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* i2c */ 74*4882a593Smuzhiyun #define CONFIG_SYS_I2C 75*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH 76*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SLAVE 0x60 77*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1 78*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_SPEED0 400000 79*4882a593Smuzhiyun #define CONFIG_SH_I2C_DATA_HIGH 4 80*4882a593Smuzhiyun #define CONFIG_SH_I2C_DATA_LOW 5 81*4882a593Smuzhiyun #define CONFIG_SH_I2C_CLOCK 10000000 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* USB */ 86*4882a593Smuzhiyun #ifdef CONFIG_R8A7795 87*4882a593Smuzhiyun #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 88*4882a593Smuzhiyun #else 89*4882a593Smuzhiyun #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 90*4882a593Smuzhiyun #endif 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* SDHI */ 93*4882a593Smuzhiyun #define CONFIG_SH_SDHI_FREQ 200000000 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* Environment in eMMC, at the end of 2nd "boot sector" */ 96*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) 97*4882a593Smuzhiyun #define CONFIG_SYS_MMC_ENV_DEV 1 98*4882a593Smuzhiyun #define CONFIG_SYS_MMC_ENV_PART 2 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* Module stop status bits */ 101*4882a593Smuzhiyun /* MFIS, SCIF1 */ 102*4882a593Smuzhiyun #define CONFIG_SMSTP2_ENA 0x00002040 103*4882a593Smuzhiyun /* SCIF2 */ 104*4882a593Smuzhiyun #define CONFIG_SMSTP3_ENA 0x00000400 105*4882a593Smuzhiyun /* INTC-AP, IRQC */ 106*4882a593Smuzhiyun #define CONFIG_SMSTP4_ENA 0x00000180 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #endif /* __ULCB_H */ 109