1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015, Savoir-faire Linux Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Derived from MX51EVK code by 5*4882a593Smuzhiyun * Guennadi Liakhovetski <lg@denx.de> 6*4882a593Smuzhiyun * Freescale Semiconductor, Inc. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Configuration settings for the TS4800 Board 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef __CONFIG_H 14*4882a593Smuzhiyun #define __CONFIG_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* High Level Configuration Options */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage bootloader */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define CONFIG_HW_WATCHDOG 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define CONFIG_MACH_TYPE MACH_TYPE_TS48XX 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* text base address used when linking */ 25*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x90008000 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #include <asm/arch/imx-regs.h> 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* enable passing of ATAGs */ 30*4882a593Smuzhiyun #define CONFIG_CMDLINE_TAG 31*4882a593Smuzhiyun #define CONFIG_SETUP_MEMORY_TAGS 32*4882a593Smuzhiyun #define CONFIG_INITRD_TAG 33*4882a593Smuzhiyun #define CONFIG_REVISION_TAG 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * Size of malloc() pool 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* 41*4882a593Smuzhiyun * Hardware drivers 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define CONFIG_MXC_UART 45*4882a593Smuzhiyun #define CONFIG_MXC_UART_BASE UART1_BASE 46*4882a593Smuzhiyun #define CONFIG_MXC_GPIO 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * SPI Configs 50*4882a593Smuzhiyun * */ 51*4882a593Smuzhiyun #define CONFIG_HARD_SPI /* puts SPI: ready */ 52*4882a593Smuzhiyun #define CONFIG_MXC_SPI /* driver for the SPI controllers*/ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* 55*4882a593Smuzhiyun * MMC Configs 56*4882a593Smuzhiyun * */ 57*4882a593Smuzhiyun #define CONFIG_FSL_ESDHC 58*4882a593Smuzhiyun #define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* 61*4882a593Smuzhiyun * Eth Configs 62*4882a593Smuzhiyun */ 63*4882a593Smuzhiyun #define CONFIG_MII 64*4882a593Smuzhiyun #define CONFIG_PHY_SMSC 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define CONFIG_FEC_MXC 67*4882a593Smuzhiyun #define IMX_FEC_BASE FEC_BASE_ADDR 68*4882a593Smuzhiyun #define CONFIG_ETHPRIME "FEC" 69*4882a593Smuzhiyun #define CONFIG_FEC_MXC_PHYADDR 0 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* allow to overwrite serial and ethaddr */ 72*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE /* disable vendor parameters protection (serial#, ethaddr) */ 73*4882a593Smuzhiyun #define CONFIG_CONS_INDEX 1 /* use UART0 : used by serial driver */ 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /*********************************************************** 76*4882a593Smuzhiyun * Command definition 77*4882a593Smuzhiyun ***********************************************************/ 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* Environment variables */ 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define CONFIG_LOADADDR 0x91000000 /* loadaddr env var */ 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 85*4882a593Smuzhiyun "script=boot.scr\0" \ 86*4882a593Smuzhiyun "image=zImage\0" \ 87*4882a593Smuzhiyun "fdt_file=imx51-ts4800.dtb\0" \ 88*4882a593Smuzhiyun "fdt_addr=0x90fe0000\0" \ 89*4882a593Smuzhiyun "mmcdev=0\0" \ 90*4882a593Smuzhiyun "mmcpart=2\0" \ 91*4882a593Smuzhiyun "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \ 92*4882a593Smuzhiyun "mmcargs=setenv bootargs root=${mmcroot}\0" \ 93*4882a593Smuzhiyun "addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \ 94*4882a593Smuzhiyun "loadbootscript=" \ 95*4882a593Smuzhiyun "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 96*4882a593Smuzhiyun "bootscript=echo Running bootscript from mmc ...; " \ 97*4882a593Smuzhiyun "source\0" \ 98*4882a593Smuzhiyun "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \ 99*4882a593Smuzhiyun "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 100*4882a593Smuzhiyun "mmcboot=echo Booting from mmc ...; " \ 101*4882a593Smuzhiyun "run mmcargs addtty; " \ 102*4882a593Smuzhiyun "if run loadfdt; then " \ 103*4882a593Smuzhiyun "bootz ${loadaddr} - ${fdt_addr}; " \ 104*4882a593Smuzhiyun "else " \ 105*4882a593Smuzhiyun "echo ERR: cannot load FDT; " \ 106*4882a593Smuzhiyun "fi; " 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND \ 110*4882a593Smuzhiyun "mmc dev ${mmcdev}; if mmc rescan; then " \ 111*4882a593Smuzhiyun "if run loadbootscript; then " \ 112*4882a593Smuzhiyun "run bootscript; " \ 113*4882a593Smuzhiyun "else " \ 114*4882a593Smuzhiyun "if run loadimage; then " \ 115*4882a593Smuzhiyun "run mmcboot; " \ 116*4882a593Smuzhiyun "fi; " \ 117*4882a593Smuzhiyun "fi; " \ 118*4882a593Smuzhiyun "fi; " 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* 121*4882a593Smuzhiyun * Miscellaneous configurable options 122*4882a593Smuzhiyun */ 123*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP /* undef to save memory */ 124*4882a593Smuzhiyun #define CONFIG_AUTO_COMPLETE 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /*----------------------------------------------------------------------- 131*4882a593Smuzhiyun * Physical Memory Map 132*4882a593Smuzhiyun */ 133*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 134*4882a593Smuzhiyun #define PHYS_SDRAM_1 CSD0_BASE_ADDR 135*4882a593Smuzhiyun #define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) 138*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) 139*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_OFFSET \ 142*4882a593Smuzhiyun (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 143*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR \ 144*4882a593Smuzhiyun (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* Low level init */ 147*4882a593Smuzhiyun #define CONFIG_SYS_DDR_CLKSEL 0 148*4882a593Smuzhiyun #define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 149*4882a593Smuzhiyun #define CONFIG_SYS_MAIN_PWR_ON 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun /*----------------------------------------------------------------------- 152*4882a593Smuzhiyun * Environment organization 153*4882a593Smuzhiyun */ 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (6 * 64 * 1024) 156*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (8 * 1024) 157*4882a593Smuzhiyun #define CONFIG_SYS_MMC_ENV_DEV 0 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #endif 160