1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2013 3*4882a593Smuzhiyun * Texas Instruments Incorporated. 4*4882a593Smuzhiyun * Sricharan R <r.sricharan@ti.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Derived from OMAP4 done by: 7*4882a593Smuzhiyun * Aneesh V <aneesh@ti.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * TI OMAP5 AND DRA7XX common configuration settings 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * For more details, please see the technical documents listed at 14*4882a593Smuzhiyun * http://www.ti.com/product/omap5432 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef __CONFIG_TI_OMAP5_COMMON_H 18*4882a593Smuzhiyun #define __CONFIG_TI_OMAP5_COMMON_H 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Use General purpose timer 1 */ 21*4882a593Smuzhiyun #define CONFIG_SYS_TIMERBASE GPT2_BASE 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* 24*4882a593Smuzhiyun * For the DDR timing information we can either dynamically determine 25*4882a593Smuzhiyun * the timings to use or use pre-determined timings (based on using the 26*4882a593Smuzhiyun * dynamic method. Default to the static timing infomation. 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 29*4882a593Smuzhiyun #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 30*4882a593Smuzhiyun #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION 31*4882a593Smuzhiyun #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS 32*4882a593Smuzhiyun #endif 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define CONFIG_PALMAS_POWER 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #include <asm/arch/cpu.h> 37*4882a593Smuzhiyun #include <asm/arch/omap.h> 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #include <configs/ti_armv7_omap.h> 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* 42*4882a593Smuzhiyun * Hardware drivers 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_CLK 48000000 45*4882a593Smuzhiyun #if !defined(CONFIG_DM_SERIAL) 46*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_SERIAL 47*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_REG_SIZE (-4) 48*4882a593Smuzhiyun #endif 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* 51*4882a593Smuzhiyun * Environment setup 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #ifndef DFUARGS 55*4882a593Smuzhiyun #define DFUARGS 56*4882a593Smuzhiyun #endif 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #include <environment/ti/boot.h> 59*4882a593Smuzhiyun #include <environment/ti/mmc.h> 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 62*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 63*4882a593Smuzhiyun DEFAULT_LINUX_BOOT_ENV \ 64*4882a593Smuzhiyun DEFAULT_MMC_TI_ARGS \ 65*4882a593Smuzhiyun DEFAULT_FIT_TI_ARGS \ 66*4882a593Smuzhiyun DEFAULT_COMMON_BOOT_TI_ARGS \ 67*4882a593Smuzhiyun DEFAULT_FDT_TI_ARGS \ 68*4882a593Smuzhiyun DFUARGS \ 69*4882a593Smuzhiyun NETARGS \ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* 72*4882a593Smuzhiyun * SPL related defines. The Public RAM memory map the ROM defines the 73*4882a593Smuzhiyun * area between 0x40300000 and 0x4031E000 as a download area for OMAP5. 74*4882a593Smuzhiyun * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000. 75*4882a593Smuzhiyun * We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and 76*4882a593Smuzhiyun * print some information. 77*4882a593Smuzhiyun */ 78*4882a593Smuzhiyun #ifdef CONFIG_TI_SECURE_DEVICE 79*4882a593Smuzhiyun /* 80*4882a593Smuzhiyun * For memory booting on HS parts, the first 4KB of the internal RAM is 81*4882a593Smuzhiyun * reserved for secure world use and the flash loader image is 82*4882a593Smuzhiyun * preceded by a secure certificate. The SPL will therefore run in internal 83*4882a593Smuzhiyun * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)). 84*4882a593Smuzhiyun */ 85*4882a593Smuzhiyun #define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000 86*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE 0x40301350 87*4882a593Smuzhiyun /* If no specific start address is specified then the secure EMIF 88*4882a593Smuzhiyun * region will be placed at the end of the DDR space. In order to prevent 89*4882a593Smuzhiyun * the main u-boot relocation from clobbering that memory and causing a 90*4882a593Smuzhiyun * firewall violation, we tell u-boot that memory is protected RAM (PRAM) 91*4882a593Smuzhiyun */ 92*4882a593Smuzhiyun #if (CONFIG_TI_SECURE_EMIF_REGION_START == 0) 93*4882a593Smuzhiyun #define CONFIG_PRAM (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE) >> 10 94*4882a593Smuzhiyun #endif 95*4882a593Smuzhiyun #else 96*4882a593Smuzhiyun /* 97*4882a593Smuzhiyun * For all booting on GP parts, the flash loader image is 98*4882a593Smuzhiyun * downloaded into internal RAM at address 0x40300000. 99*4882a593Smuzhiyun */ 100*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE 0x40300000 101*4882a593Smuzhiyun #endif 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ 104*4882a593Smuzhiyun (128 << 20)) 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD 107*4882a593Smuzhiyun #undef CONFIG_TIMER 108*4882a593Smuzhiyun #endif 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #endif /* __CONFIG_TI_OMAP5_COMMON_H */ 111