1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * ti_omap3_common.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * For more details, please see the technical documents listed at 9*4882a593Smuzhiyun * http://www.ti.com/product/omap3530 10*4882a593Smuzhiyun * http://www.ti.com/product/omap3630 11*4882a593Smuzhiyun * http://www.ti.com/product/dm3730 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef __CONFIG_TI_OMAP3_COMMON_H__ 15*4882a593Smuzhiyun #define __CONFIG_TI_OMAP3_COMMON_H__ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * High Level Configuration Options 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #include <asm/arch/cpu.h> 22*4882a593Smuzhiyun #include <asm/arch/omap.h> 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* The chip has SDRC controller */ 25*4882a593Smuzhiyun #define CONFIG_SDRC 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Clock Defines */ 28*4882a593Smuzhiyun #define V_OSCK 26000000 /* Clock output from T2 */ 29*4882a593Smuzhiyun #define V_SCLK (V_OSCK >> 1) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* NS16550 Configuration */ 32*4882a593Smuzhiyun #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 33*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 34*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD 35*4882a593Smuzhiyun # define CONFIG_SYS_NS16550_SERIAL 36*4882a593Smuzhiyun # define CONFIG_SYS_NS16550_REG_SIZE (-4) 37*4882a593Smuzhiyun #endif 38*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 39*4882a593Smuzhiyun 115200} 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Select serial console configuration */ 42*4882a593Smuzhiyun #define CONFIG_CONS_INDEX 3 43*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD 44*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 45*4882a593Smuzhiyun #define CONFIG_SERIAL3 3 46*4882a593Smuzhiyun #endif 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* Physical Memory Map */ 49*4882a593Smuzhiyun #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 50*4882a593Smuzhiyun #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* 53*4882a593Smuzhiyun * OMAP3 has 12 GP timers, they can be driven by the system clock 54*4882a593Smuzhiyun * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 55*4882a593Smuzhiyun * This rate is divided by a local divisor. 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (256 << 10) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* SPL */ 62*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE 0x40200800 63*4882a593Smuzhiyun #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ 64*4882a593Smuzhiyun (64 << 20)) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #ifdef CONFIG_NAND 67*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BASE 0x30000000 68*4882a593Smuzhiyun #endif 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* Now bring in the rest of the common code. */ 71*4882a593Smuzhiyun #include <configs/ti_armv7_omap.h> 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #endif /* __CONFIG_TI_OMAP3_COMMON_H__ */ 74