1*4882a593Smuzhiyun /** 2*4882a593Smuzhiyun * (C) Copyright 2014, Cavium Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun **/ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __THUNDERX_88XX_H__ 8*4882a593Smuzhiyun #define __THUNDERX_88XX_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define CONFIG_REMAKE_ELF 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CONFIG_THUNDERX 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define CONFIG_SYS_64BIT 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define MEM_BASE 0x00500000 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CONFIG_SYS_LOWMEM_BASE MEM_BASE 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Link Definitions */ 21*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x00500000 22*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* SMP Spin Table Definitions */ 25*4882a593Smuzhiyun #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Generic Timer Definitions */ 28*4882a593Smuzhiyun #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START MEM_BASE 31*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Size of malloc() pool */ 34*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* PL011 Serial Configuration */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define CONFIG_PL01X_SERIAL 39*4882a593Smuzhiyun #define CONFIG_PL011_CLOCK 24000000 40*4882a593Smuzhiyun #define CONFIG_CONS_INDEX 1 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* Generic Interrupt Controller Definitions */ 43*4882a593Smuzhiyun #define GICD_BASE (0x801000000000) 44*4882a593Smuzhiyun #define GICR_BASE (0x801000002000) 45*4882a593Smuzhiyun #define CONFIG_SYS_SERIAL0 0x87e024000000 46*4882a593Smuzhiyun #define CONFIG_SYS_SERIAL1 0x87e025000000 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* BOOTP options */ 49*4882a593Smuzhiyun #define CONFIG_BOOTP_BOOTFILESIZE 50*4882a593Smuzhiyun #define CONFIG_BOOTP_BOOTPATH 51*4882a593Smuzhiyun #define CONFIG_BOOTP_GATEWAY 52*4882a593Smuzhiyun #define CONFIG_BOOTP_HOSTNAME 53*4882a593Smuzhiyun #define CONFIG_BOOTP_PXE 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* Miscellaneous configurable options */ 56*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (MEM_BASE) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Physical Memory Map */ 59*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 60*4882a593Smuzhiyun #define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */ 61*4882a593Smuzhiyun #define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */ 62*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Initial environment variables */ 65*4882a593Smuzhiyun #define UBOOT_IMG_HEAD_SIZE 0x40 66*4882a593Smuzhiyun /* C80000 - 0x40 */ 67*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 68*4882a593Smuzhiyun "kernel_addr=08007ffc0\0" \ 69*4882a593Smuzhiyun "fdt_addr=0x94C00000\0" \ 70*4882a593Smuzhiyun "fdt_high=0x9fffffff\0" 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* Do not preserve environment */ 73*4882a593Smuzhiyun #define CONFIG_ENV_SIZE 0x1000 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* Monitor Command Prompt */ 76*4882a593Smuzhiyun #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 77*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 78*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 1 79*4882a593Smuzhiyun #define CONFIG_SYS_MAXARGS 64 /* max command args */ 80*4882a593Smuzhiyun #define CONFIG_NO_RELOCATION 1 81*4882a593Smuzhiyun #define CONFIG_LIB_RAND 82*4882a593Smuzhiyun #define PLL_REF_CLK 50000000 /* 50 MHz */ 83*4882a593Smuzhiyun #define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #endif /* __THUNDERX_88XX_H__ */ 86