1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _CONFIG_THEADORABLE_H 8*4882a593Smuzhiyun #define _CONFIG_THEADORABLE_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * High Level Configuration Options (easy to change) 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun #define CONFIG_DISPLAY_BOARDINFO_LATE 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 17*4882a593Smuzhiyun * for DDR ECC byte filling in the SPL before loading the main 18*4882a593Smuzhiyun * U-Boot into it. 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x00800000 21*4882a593Smuzhiyun #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* 24*4882a593Smuzhiyun * Commands configuration 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * The debugging version enables USB support via defconfig. 29*4882a593Smuzhiyun * This version should also enable all other non-production 30*4882a593Smuzhiyun * interfaces / features. 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* I2C */ 34*4882a593Smuzhiyun #define CONFIG_SYS_I2C 35*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MVTWSI 36*4882a593Smuzhiyun #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 37*4882a593Smuzhiyun #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE 38*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SLAVE 0x0 39*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SPEED 100000 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* USB/EHCI configuration */ 42*4882a593Smuzhiyun #define CONFIG_EHCI_IS_TDI 43*4882a593Smuzhiyun #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* SPI NOR flash default params, used by sf commands */ 46*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_SPEED 27777777 /* for fast SPL booting */ 47*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Environment in SPI NOR flash */ 50*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 51*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 52*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ 53*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 56*4882a593Smuzhiyun #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define CONFIG_SYS_ALT_MEMTEST 59*4882a593Smuzhiyun #define CONFIG_PREBOOT 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* Keep device tree and initrd in lower memory so the kernel can access them */ 62*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 63*4882a593Smuzhiyun "fdt_high=0x10000000\0" \ 64*4882a593Smuzhiyun "initrd_high=0x10000000\0" 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* SATA support */ 67*4882a593Smuzhiyun #define CONFIG_SYS_SATA_MAX_DEVICE 1 68*4882a593Smuzhiyun #define CONFIG_SATA_MV 69*4882a593Smuzhiyun #define CONFIG_LIBATA 70*4882a593Smuzhiyun #define CONFIG_LBA48 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* Additional FS support/configuration */ 73*4882a593Smuzhiyun #define CONFIG_SUPPORT_VFAT 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* PCIe support */ 76*4882a593Smuzhiyun #ifdef CONFIG_CMD_PCI 77*4882a593Smuzhiyun #ifndef CONFIG_SPL_BUILD 78*4882a593Smuzhiyun #define CONFIG_PCI_MVEBU 79*4882a593Smuzhiyun #endif 80*4882a593Smuzhiyun #endif 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* Enable LCD and reserve 512KB from top of memory*/ 83*4882a593Smuzhiyun #define CONFIG_SYS_MEM_TOP_HIDE 0x80000 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* FPGA programming support */ 86*4882a593Smuzhiyun #define CONFIG_FPGA_STRATIX_V 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* 89*4882a593Smuzhiyun * Bootcounter 90*4882a593Smuzhiyun */ 91*4882a593Smuzhiyun #define CONFIG_BOOTCOUNT_LIMIT 92*4882a593Smuzhiyun #define CONFIG_BOOTCOUNT_RAM 93*4882a593Smuzhiyun /* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */ 94*4882a593Smuzhiyun #define BOOTCOUNT_ADDR 0x1000 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* 97*4882a593Smuzhiyun * mv-common.h should be defined after CMD configs since it used them 98*4882a593Smuzhiyun * to enable certain macros 99*4882a593Smuzhiyun */ 100*4882a593Smuzhiyun #include "mv-common.h" 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* 103*4882a593Smuzhiyun * Memory layout while starting into the bin_hdr via the 104*4882a593Smuzhiyun * BootROM: 105*4882a593Smuzhiyun * 106*4882a593Smuzhiyun * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 107*4882a593Smuzhiyun * 0x4000.4030 bin_hdr start address 108*4882a593Smuzhiyun * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 109*4882a593Smuzhiyun * 0x4007.fffc BootROM stack top 110*4882a593Smuzhiyun * 111*4882a593Smuzhiyun * The address space between 0x4007.fffc and 0x400f.fff is not locked in 112*4882a593Smuzhiyun * L2 cache thus cannot be used. 113*4882a593Smuzhiyun */ 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* SPL */ 116*4882a593Smuzhiyun /* Defines for SPL */ 117*4882a593Smuzhiyun #define CONFIG_SPL_FRAMEWORK 118*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE 0x40004030 119*4882a593Smuzhiyun #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 122*4882a593Smuzhiyun #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD 125*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_SIMPLE 126*4882a593Smuzhiyun #endif 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 129*4882a593Smuzhiyun #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* SPL related SPI defines */ 132*4882a593Smuzhiyun #define CONFIG_SPL_SPI_LOAD 133*4882a593Smuzhiyun #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000 134*4882a593Smuzhiyun #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 137*4882a593Smuzhiyun #define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */ 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun #endif /* _CONFIG_THEADORABLE_H */ 140