1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010-2012 3*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _TEGRA20_COMMON_H_ 9*4882a593Smuzhiyun #define _TEGRA20_COMMON_H_ 10*4882a593Smuzhiyun #include "tegra-common.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * NS16550 Configuration 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * Miscellaneous configurable options 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun #define CONFIG_STACKBASE 0x02800000 /* 40MB */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /*----------------------------------------------------------------------- 23*4882a593Smuzhiyun * Physical Memory Map 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x00110000 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * Memory layout for where various images get loaded by boot scripts: 29*4882a593Smuzhiyun * 30*4882a593Smuzhiyun * scriptaddr can be pretty much anywhere that doesn't conflict with something 31*4882a593Smuzhiyun * else. Put it above BOOTMAPSZ to eliminate conflicts. 32*4882a593Smuzhiyun * 33*4882a593Smuzhiyun * pxefile_addr_r can be pretty much anywhere that doesn't conflict with 34*4882a593Smuzhiyun * something else. Put it above BOOTMAPSZ to eliminate conflicts. 35*4882a593Smuzhiyun * 36*4882a593Smuzhiyun * kernel_addr_r must be within the first 128M of RAM in order for the 37*4882a593Smuzhiyun * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will 38*4882a593Smuzhiyun * decompress itself to 0x8000 after the start of RAM, kernel_addr_r 39*4882a593Smuzhiyun * should not overlap that area, or the kernel will have to copy itself 40*4882a593Smuzhiyun * somewhere else before decompression. Similarly, the address of any other 41*4882a593Smuzhiyun * data passed to the kernel shouldn't overlap the start of RAM. Pushing 42*4882a593Smuzhiyun * this up to 16M allows for a sizable kernel to be decompressed below the 43*4882a593Smuzhiyun * compressed load address. 44*4882a593Smuzhiyun * 45*4882a593Smuzhiyun * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for 46*4882a593Smuzhiyun * the compressed kernel to be up to 16M too. 47*4882a593Smuzhiyun * 48*4882a593Smuzhiyun * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows 49*4882a593Smuzhiyun * for the FDT/DTB to be up to 1M, which is hopefully plenty. 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun #define CONFIG_LOADADDR 0x01000000 52*4882a593Smuzhiyun #define MEM_LAYOUT_ENV_SETTINGS \ 53*4882a593Smuzhiyun "scriptaddr=0x10000000\0" \ 54*4882a593Smuzhiyun "pxefile_addr_r=0x10100000\0" \ 55*4882a593Smuzhiyun "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ 56*4882a593Smuzhiyun "fdt_addr_r=0x02000000\0" \ 57*4882a593Smuzhiyun "ramdisk_addr_r=0x02100000\0" 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Defines for SPL */ 60*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE 0x00108000 61*4882a593Smuzhiyun #define CONFIG_SYS_SPL_MALLOC_START 0x00090000 62*4882a593Smuzhiyun #define CONFIG_SPL_STACK 0x000ffffc 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Align LCD to 1MB boundary */ 65*4882a593Smuzhiyun #define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #ifdef CONFIG_TEGRA_LP0 68*4882a593Smuzhiyun #define TEGRA_LP0_ADDR 0x1C406000 69*4882a593Smuzhiyun #define TEGRA_LP0_SIZE 0x2000 70*4882a593Smuzhiyun #define TEGRA_LP0_VEC \ 71*4882a593Smuzhiyun "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \ 72*4882a593Smuzhiyun "@" __stringify(TEGRA_LP0_ADDR) " " 73*4882a593Smuzhiyun #else 74*4882a593Smuzhiyun #define TEGRA_LP0_VEC 75*4882a593Smuzhiyun #endif 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* 78*4882a593Smuzhiyun * This parameter affects a TXFILLTUNING field that controls how much data is 79*4882a593Smuzhiyun * sent to the latency fifo before it is sent to the wire. Without this 80*4882a593Smuzhiyun * parameter, the default (2) causes occasional Data Buffer Errors in OUT 81*4882a593Smuzhiyun * packets depending on the buffer address and size. 82*4882a593Smuzhiyun */ 83*4882a593Smuzhiyun #define CONFIG_USB_EHCI_TXFIFO_THRESH 10 84*4882a593Smuzhiyun #define CONFIG_EHCI_IS_TDI 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define CONFIG_SYS_NAND_SELF_INIT 87*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ONFI_DETECTION 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #endif /* _TEGRA20_COMMON_H_ */ 90