1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010-2012 3*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _TEGRA_COMMON_H_ 9*4882a593Smuzhiyun #define _TEGRA_COMMON_H_ 10*4882a593Smuzhiyun #include <linux/sizes.h> 11*4882a593Smuzhiyun #include <linux/stringify.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * High Level Configuration Options 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun #define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */ 17*4882a593Smuzhiyun #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #include <asm/arch/tegra.h> /* get chip and board defs */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */ 22*4882a593Smuzhiyun #ifndef CONFIG_ARM64 23*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_RATE 1000000 24*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE 25*4882a593Smuzhiyun #endif 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Environment */ 30*4882a593Smuzhiyun #define CONFIG_ENV_VARS_UBOOT_CONFIG 31*4882a593Smuzhiyun #define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * NS16550 Configuration 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* 39*4882a593Smuzhiyun * Common HW configuration. 40*4882a593Smuzhiyun * If this varies between SoCs later, move to tegraNN-common.h 41*4882a593Smuzhiyun * Note: This is number of devices, not max device ID. 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun #define CONFIG_SYS_MMC_MAX_DEVICE 4 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* 46*4882a593Smuzhiyun * select serial console configuration 47*4882a593Smuzhiyun */ 48*4882a593Smuzhiyun #define CONFIG_CONS_INDEX 1 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* allow to overwrite serial and ethaddr */ 51*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* turn on command-line edit/hist/auto */ 54*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* 57*4882a593Smuzhiyun * Increasing the size of the IO buffer as default nfsargs size is more 58*4882a593Smuzhiyun * than 256 and so it is not possible to edit it 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun #define CONFIG_SYS_CBSIZE (1024 * 2) /* Console I/O Buffer Size */ 61*4882a593Smuzhiyun /* Print Buffer Size */ 62*4882a593Smuzhiyun #define CONFIG_SYS_MAXARGS 64 /* max number of command args */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Boot Argument Buffer Size */ 65*4882a593Smuzhiyun #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) 68*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /*----------------------------------------------------------------------- 71*4882a593Smuzhiyun * Physical Memory Map 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 2 74*4882a593Smuzhiyun #define PHYS_SDRAM_1 NV_PA_SDRC_CS0 75*4882a593Smuzhiyun #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE 78*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE 83*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN 84*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 85*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_SIZE - \ 86*4882a593Smuzhiyun GENERATED_GBL_DATA_SIZE) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* Defines for SPL */ 89*4882a593Smuzhiyun #define CONFIG_SPL_FRAMEWORK 90*4882a593Smuzhiyun #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \ 91*4882a593Smuzhiyun CONFIG_SPL_TEXT_BASE) 92*4882a593Smuzhiyun #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* Misc utility code */ 95*4882a593Smuzhiyun #define CONFIG_BOUNCE_BUFFER 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #ifndef CONFIG_SPL_BUILD 98*4882a593Smuzhiyun #include <config_distro_defaults.h> 99*4882a593Smuzhiyun #endif 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #endif /* _TEGRA_COMMON_H_ */ 102