1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2011 3*4882a593Smuzhiyun * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2009 TechNexion Ltd. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __TAM3517_H 11*4882a593Smuzhiyun #define __TAM3517_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * High Level Configuration Options 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x80008000 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #include <asm/arch/cpu.h> /* get chip and board defs */ 22*4882a593Smuzhiyun #include <asm/arch/omap.h> 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* Clock Defines */ 25*4882a593Smuzhiyun #define V_OSCK 26000000 /* Clock output from T2 */ 26*4882a593Smuzhiyun #define V_SCLK (V_OSCK >> 1) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define CONFIG_MISC_INIT_R 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 31*4882a593Smuzhiyun #define CONFIG_SETUP_MEMORY_TAGS 32*4882a593Smuzhiyun #define CONFIG_INITRD_TAG 33*4882a593Smuzhiyun #define CONFIG_REVISION_TAG 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * Size of malloc() pool 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 39*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ 40*4882a593Smuzhiyun 2 * 1024 * 1024) 41*4882a593Smuzhiyun /* 42*4882a593Smuzhiyun * DDR related 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * Hardware drivers 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* 51*4882a593Smuzhiyun * NS16550 Configuration 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_SERIAL 54*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_REG_SIZE (-4) 55*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* 58*4882a593Smuzhiyun * select serial console configuration 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun #define CONFIG_CONS_INDEX 1 61*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 62*4882a593Smuzhiyun #define CONFIG_SERIAL1 /* UART1 */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* allow to overwrite serial and ethaddr */ 65*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 66*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 67*4882a593Smuzhiyun 115200} 68*4882a593Smuzhiyun /* EHCI */ 69*4882a593Smuzhiyun #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define CONFIG_SYS_I2C 72*4882a593Smuzhiyun #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 73*4882a593Smuzhiyun #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 74*4882a593Smuzhiyun #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ 75*4882a593Smuzhiyun #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 76*4882a593Smuzhiyun #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* 79*4882a593Smuzhiyun * Board NAND Info. 80*4882a593Smuzhiyun */ 81*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 82*4882a593Smuzhiyun /* to access */ 83*4882a593Smuzhiyun /* nand at CS0 */ 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 86*4882a593Smuzhiyun /* NAND devices */ 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #define CONFIG_AUTO_COMPLETE 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* 91*4882a593Smuzhiyun * Miscellaneous configurable options 92*4882a593Smuzhiyun */ 93*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP /* undef to save memory */ 94*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 95*4882a593Smuzhiyun #define CONFIG_AUTO_COMPLETE 96*4882a593Smuzhiyun #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 99*4882a593Smuzhiyun /* args */ 100*4882a593Smuzhiyun /* memtest works on */ 101*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 102*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 103*4882a593Smuzhiyun 0x01F00000) /* 31MB */ 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 106*4882a593Smuzhiyun /* address */ 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* 109*4882a593Smuzhiyun * AM3517 has 12 GP timers, they can be driven by the system clock 110*4882a593Smuzhiyun * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 111*4882a593Smuzhiyun * This rate is divided by a local divisor. 112*4882a593Smuzhiyun */ 113*4882a593Smuzhiyun #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 114*4882a593Smuzhiyun #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* 117*4882a593Smuzhiyun * Physical Memory Map 118*4882a593Smuzhiyun */ 119*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 120*4882a593Smuzhiyun #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 121*4882a593Smuzhiyun #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /* 124*4882a593Smuzhiyun * FLASH and environment organization 125*4882a593Smuzhiyun */ 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /* **** PISMO SUPPORT *** */ 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /* Redundant Environment */ 130*4882a593Smuzhiyun #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 131*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 132*4882a593Smuzhiyun #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 133*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 134*4882a593Smuzhiyun 2 * CONFIG_SYS_ENV_SECT_SIZE) 135*4882a593Smuzhiyun #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 138*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 139*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_SIZE 0x800 140*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 141*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_SIZE - \ 142*4882a593Smuzhiyun GENERATED_GBL_DATA_SIZE) 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun /* 145*4882a593Smuzhiyun * ethernet support, EMAC 146*4882a593Smuzhiyun * 147*4882a593Smuzhiyun */ 148*4882a593Smuzhiyun #define CONFIG_DRIVER_TI_EMAC 149*4882a593Smuzhiyun #define CONFIG_DRIVER_TI_EMAC_USE_RMII 150*4882a593Smuzhiyun #define CONFIG_MII 151*4882a593Smuzhiyun #define CONFIG_BOOTP_DNS 152*4882a593Smuzhiyun #define CONFIG_BOOTP_DNS2 153*4882a593Smuzhiyun #define CONFIG_BOOTP_SEND_HOSTNAME 154*4882a593Smuzhiyun #define CONFIG_NET_RETRY_COUNT 10 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /* Defines for SPL */ 157*4882a593Smuzhiyun #define CONFIG_SPL_FRAMEWORK 158*4882a593Smuzhiyun #define CONFIG_SPL_CONSOLE 159*4882a593Smuzhiyun #define CONFIG_SPL_NAND_SOFTECC 160*4882a593Smuzhiyun #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun #define CONFIG_SPL_NAND_BASE 163*4882a593Smuzhiyun #define CONFIG_SPL_NAND_DRIVERS 164*4882a593Smuzhiyun #define CONFIG_SPL_NAND_ECC 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 167*4882a593Smuzhiyun #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 168*4882a593Smuzhiyun CONFIG_SPL_TEXT_BASE) 169*4882a593Smuzhiyun #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 172*4882a593Smuzhiyun #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 173*4882a593Smuzhiyun #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 174*4882a593Smuzhiyun #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 177*4882a593Smuzhiyun #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun /* FAT */ 180*4882a593Smuzhiyun #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" 181*4882a593Smuzhiyun #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun /* RAW SD card / eMMC */ 184*4882a593Smuzhiyun #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ 185*4882a593Smuzhiyun #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ 186*4882a593Smuzhiyun #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun /* NAND boot config */ 189*4882a593Smuzhiyun #define CONFIG_SYS_NAND_PAGE_COUNT 64 190*4882a593Smuzhiyun #define CONFIG_SYS_NAND_PAGE_SIZE 2048 191*4882a593Smuzhiyun #define CONFIG_SYS_NAND_OOBSIZE 64 192*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 193*4882a593Smuzhiyun #define CONFIG_SYS_NAND_5_ADDR_CYCLE 194*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 195*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 196*4882a593Smuzhiyun 48, 49, 50, 51, 52, 53, 54, 55,\ 197*4882a593Smuzhiyun 56, 57, 58, 59, 60, 61, 62, 63} 198*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ECCSIZE 256 199*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ECCBYTES 3 200*4882a593Smuzhiyun #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 205*4882a593Smuzhiyun #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun /* Setup MTD for NAND on the SOM */ 208*4882a593Smuzhiyun #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 209*4882a593Smuzhiyun #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 210*4882a593Smuzhiyun "1m(u-boot),256k(env1)," \ 211*4882a593Smuzhiyun "256k(env2),6m(kernel),-(rootfs)" 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun #define CONFIG_TAM3517_SETTINGS \ 214*4882a593Smuzhiyun "netdev=eth0\0" \ 215*4882a593Smuzhiyun "nandargs=setenv bootargs root=${nandroot} " \ 216*4882a593Smuzhiyun "rootfstype=${nandrootfstype}\0" \ 217*4882a593Smuzhiyun "nfsargs=setenv bootargs root=/dev/nfs rw " \ 218*4882a593Smuzhiyun "nfsroot=${serverip}:${rootpath}\0" \ 219*4882a593Smuzhiyun "ramargs=setenv bootargs root=/dev/ram rw\0" \ 220*4882a593Smuzhiyun "addip_sta=setenv bootargs ${bootargs} " \ 221*4882a593Smuzhiyun "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 222*4882a593Smuzhiyun ":${hostname}:${netdev}:off panic=1\0" \ 223*4882a593Smuzhiyun "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 224*4882a593Smuzhiyun "addip=if test -n ${ipdyn};then run addip_dyn;" \ 225*4882a593Smuzhiyun "else run addip_sta;fi\0" \ 226*4882a593Smuzhiyun "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 227*4882a593Smuzhiyun "addtty=setenv bootargs ${bootargs}" \ 228*4882a593Smuzhiyun " console=ttyO0,${baudrate}\0" \ 229*4882a593Smuzhiyun "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 230*4882a593Smuzhiyun "loadaddr=82000000\0" \ 231*4882a593Smuzhiyun "kernel_addr_r=82000000\0" \ 232*4882a593Smuzhiyun "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 233*4882a593Smuzhiyun "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 234*4882a593Smuzhiyun "flash_self=run ramargs addip addtty addmtd addmisc;" \ 235*4882a593Smuzhiyun "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 236*4882a593Smuzhiyun "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 237*4882a593Smuzhiyun "bootm ${kernel_addr}\0" \ 238*4882a593Smuzhiyun "nandboot=run nandargs addip addtty addmtd addmisc;" \ 239*4882a593Smuzhiyun "nand read ${kernel_addr_r} kernel\0" \ 240*4882a593Smuzhiyun "bootm ${kernel_addr_r}\0" \ 241*4882a593Smuzhiyun "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 242*4882a593Smuzhiyun "run nfsargs addip addtty addmtd addmisc;" \ 243*4882a593Smuzhiyun "bootm ${kernel_addr_r}\0" \ 244*4882a593Smuzhiyun "net_self=if run net_self_load;then " \ 245*4882a593Smuzhiyun "run ramargs addip addtty addmtd addmisc;" \ 246*4882a593Smuzhiyun "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ 247*4882a593Smuzhiyun "else echo Images not loades;fi\0" \ 248*4882a593Smuzhiyun "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 249*4882a593Smuzhiyun "load=tftp ${loadaddr} ${u-boot}\0" \ 250*4882a593Smuzhiyun "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 251*4882a593Smuzhiyun "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 252*4882a593Smuzhiyun "uboot_addr=0x80000\0" \ 253*4882a593Smuzhiyun "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 254*4882a593Smuzhiyun "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 255*4882a593Smuzhiyun "updatemlo=nandecc hw;nand erase 0 20000;" \ 256*4882a593Smuzhiyun "nand write ${loadaddr} 0 20000\0" \ 257*4882a593Smuzhiyun "upd=if run load;then echo Updating u-boot;if run update;" \ 258*4882a593Smuzhiyun "then echo U-Boot updated;" \ 259*4882a593Smuzhiyun "else echo Error updating u-boot !;" \ 260*4882a593Smuzhiyun "echo Board without bootloader !!;" \ 261*4882a593Smuzhiyun "fi;" \ 262*4882a593Smuzhiyun "else echo U-Boot not downloaded..exiting;fi\0" \ 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun /* 265*4882a593Smuzhiyun * this is common code for all TAM3517 boards. 266*4882a593Smuzhiyun * MAC address is stored from manufacturer in 267*4882a593Smuzhiyun * I2C EEPROM 268*4882a593Smuzhiyun */ 269*4882a593Smuzhiyun #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 270*4882a593Smuzhiyun /* 271*4882a593Smuzhiyun * The I2C EEPROM on the TAM3517 contains 272*4882a593Smuzhiyun * mac address and production data 273*4882a593Smuzhiyun */ 274*4882a593Smuzhiyun struct tam3517_module_info { 275*4882a593Smuzhiyun char customer[48]; 276*4882a593Smuzhiyun char product[48]; 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun /* 279*4882a593Smuzhiyun * bit 0~47 : sequence number 280*4882a593Smuzhiyun * bit 48~55 : week of year, from 0. 281*4882a593Smuzhiyun * bit 56~63 : year 282*4882a593Smuzhiyun */ 283*4882a593Smuzhiyun unsigned long long sequence_number; 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun /* 286*4882a593Smuzhiyun * bit 0~7 : revision fixed 287*4882a593Smuzhiyun * bit 8~15 : revision major 288*4882a593Smuzhiyun * bit 16~31 : TNxxx 289*4882a593Smuzhiyun */ 290*4882a593Smuzhiyun unsigned int revision; 291*4882a593Smuzhiyun unsigned char eth_addr[4][8]; 292*4882a593Smuzhiyun unsigned char _rev[100]; 293*4882a593Smuzhiyun }; 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun #define TAM3517_READ_EEPROM(info, ret) \ 296*4882a593Smuzhiyun do { \ 297*4882a593Smuzhiyun i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ 298*4882a593Smuzhiyun if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ 299*4882a593Smuzhiyun (void *)info, sizeof(*info))) \ 300*4882a593Smuzhiyun ret = 1; \ 301*4882a593Smuzhiyun else \ 302*4882a593Smuzhiyun ret = 0; \ 303*4882a593Smuzhiyun } while (0) 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun #define TAM3517_READ_MAC_FROM_EEPROM(info) \ 306*4882a593Smuzhiyun do { \ 307*4882a593Smuzhiyun char buf[80], ethname[20]; \ 308*4882a593Smuzhiyun int i; \ 309*4882a593Smuzhiyun memset(buf, 0, sizeof(buf)); \ 310*4882a593Smuzhiyun for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \ 311*4882a593Smuzhiyun sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ 312*4882a593Smuzhiyun (info)->eth_addr[i][5], \ 313*4882a593Smuzhiyun (info)->eth_addr[i][4], \ 314*4882a593Smuzhiyun (info)->eth_addr[i][3], \ 315*4882a593Smuzhiyun (info)->eth_addr[i][2], \ 316*4882a593Smuzhiyun (info)->eth_addr[i][1], \ 317*4882a593Smuzhiyun (info)->eth_addr[i][0]); \ 318*4882a593Smuzhiyun \ 319*4882a593Smuzhiyun if (i) \ 320*4882a593Smuzhiyun sprintf(ethname, "eth%daddr", i); \ 321*4882a593Smuzhiyun else \ 322*4882a593Smuzhiyun strcpy(ethname, "ethaddr"); \ 323*4882a593Smuzhiyun printf("Setting %s from EEPROM with %s\n", ethname, buf);\ 324*4882a593Smuzhiyun env_set(ethname, buf); \ 325*4882a593Smuzhiyun } \ 326*4882a593Smuzhiyun } while (0) 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun /* The following macros are taken from Technexion's documentation */ 329*4882a593Smuzhiyun #define TAM3517_sequence_number(info) \ 330*4882a593Smuzhiyun ((info)->sequence_number % 0x1000000000000LL) 331*4882a593Smuzhiyun #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100) 332*4882a593Smuzhiyun #define TAM3517_year(info) ((info)->sequence_number >> 56) 333*4882a593Smuzhiyun #define TAM3517_revision_fixed(info) ((info)->revision % 0x100) 334*4882a593Smuzhiyun #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100) 335*4882a593Smuzhiyun #define TAM3517_revision_tn(info) ((info)->revision >> 16) 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun #define TAM3517_PRINT_SOM_INFO(info) \ 338*4882a593Smuzhiyun do { \ 339*4882a593Smuzhiyun printf("Vendor:%s\n", (info)->customer); \ 340*4882a593Smuzhiyun printf("SOM: %s\n", (info)->product); \ 341*4882a593Smuzhiyun printf("SeqNr: %02llu%02llu%012llu\n", \ 342*4882a593Smuzhiyun TAM3517_year(info), \ 343*4882a593Smuzhiyun TAM3517_week_of_year(info), \ 344*4882a593Smuzhiyun TAM3517_sequence_number(info)); \ 345*4882a593Smuzhiyun printf("Rev: TN%u %u.%u\n", \ 346*4882a593Smuzhiyun TAM3517_revision_tn(info), \ 347*4882a593Smuzhiyun TAM3517_revision_major(info), \ 348*4882a593Smuzhiyun TAM3517_revision_fixed(info)); \ 349*4882a593Smuzhiyun } while (0) 350*4882a593Smuzhiyun 351*4882a593Smuzhiyun #endif 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun #endif /* __TAM3517_H */ 354