1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2014 3*4882a593Smuzhiyun * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __CONFIG_STV0991_H 9*4882a593Smuzhiyun #define __CONFIG_STV0991_H 10*4882a593Smuzhiyun #define CONFIG_SYS_DCACHE_OFF 11*4882a593Smuzhiyun #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define CONFIG_SYS_CORTEX_R4 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* ram memory-related information */ 16*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 17*4882a593Smuzhiyun #define PHYS_SDRAM_1 0x00000000 18*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 19*4882a593Smuzhiyun #define PHYS_SDRAM_1_SIZE 0x00198000 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define CONFIG_ENV_SIZE 0x10000 22*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE 23*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET 0x30000 24*4882a593Smuzhiyun #define CONFIG_ENV_ADDR \ 25*4882a593Smuzhiyun (PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE) 26*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* serial port (PL011) configuration */ 29*4882a593Smuzhiyun #define CONFIG_PL01X_SERIAL 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* user interface */ 32*4882a593Smuzhiyun #define CONFIG_SYS_CBSIZE 1024 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* MISC */ 35*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0x00000000 36*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 37*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_ADDR 0x00190000 38*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_OFFSET \ 39*4882a593Smuzhiyun (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 40*4882a593Smuzhiyun /* U-Boot Load Address */ 41*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x00010000 42*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR \ 43*4882a593Smuzhiyun (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* GMAC related configs */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define CONFIG_MII 48*4882a593Smuzhiyun #define CONFIG_DW_ALTDESCRIPTOR 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* Command support defines */ 51*4882a593Smuzhiyun #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START 0x0000 54*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END 1024*1024 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* Misc configuration */ 57*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 58*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND "go 0x40040000" 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* 63*4882a593Smuzhiyun + * QSPI support 64*4882a593Smuzhiyun + */ 65*4882a593Smuzhiyun #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ 66*4882a593Smuzhiyun #define CONFIG_CQSPI_DECODER 0 67*4882a593Smuzhiyun #define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #endif /* __CONFIG_H */ 72