1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * include/configs/stout.h 3*4882a593Smuzhiyun * This file is Stout board configuration. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2015 Renesas Electronics Europe GmbH 6*4882a593Smuzhiyun * Copyright (C) 2015 Renesas Electronics Corporation 7*4882a593Smuzhiyun * Copyright (C) 2015 Cogent Embedded, Inc. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __STOUT_H 13*4882a593Smuzhiyun #define __STOUT_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #undef DEBUG 16*4882a593Smuzhiyun #define CONFIG_R8A7790 17*4882a593Smuzhiyun #define CONFIG_ARCH_RMOBILE_BOARD_STRING "Stout" 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #include "rcar-gen2-common.h" 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) 22*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0xB0000000 23*4882a593Smuzhiyun #else 24*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0xE8080000 25*4882a593Smuzhiyun #endif 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* STACK */ 28*4882a593Smuzhiyun #if defined(CONFIGF_RMOBILE_EXTRAM_BOOT) 29*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC 30*4882a593Smuzhiyun #else 31*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC 32*4882a593Smuzhiyun #endif 33*4882a593Smuzhiyun #define STACK_AREA_SIZE 0xC000 34*4882a593Smuzhiyun #define LOW_LEVEL_MERAM_STACK \ 35*4882a593Smuzhiyun (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* MEMORY */ 38*4882a593Smuzhiyun #define RCAR_GEN2_SDRAM_BASE 0x40000000 39*4882a593Smuzhiyun #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) 40*4882a593Smuzhiyun #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* SCIF */ 43*4882a593Smuzhiyun #define CONFIG_SCIF_A 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* SPI */ 46*4882a593Smuzhiyun #define CONFIG_SPI_FLASH_QUAD 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* SH Ether */ 49*4882a593Smuzhiyun #define CONFIG_SH_ETHER 50*4882a593Smuzhiyun #define CONFIG_SH_ETHER_USE_PORT 0 51*4882a593Smuzhiyun #define CONFIG_SH_ETHER_PHY_ADDR 0x1 52*4882a593Smuzhiyun #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII 53*4882a593Smuzhiyun #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 54*4882a593Smuzhiyun #define CONFIG_SH_ETHER_CACHE_WRITEBACK 55*4882a593Smuzhiyun #define CONFIG_SH_ETHER_CACHE_INVALIDATE 56*4882a593Smuzhiyun #define CONFIG_BITBANGMII 57*4882a593Smuzhiyun #define CONFIG_BITBANGMII_MULTI 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* I2C */ 60*4882a593Smuzhiyun #define CONFIG_SYS_I2C 61*4882a593Smuzhiyun #define CONFIG_SYS_I2C_RCAR 62*4882a593Smuzhiyun #define CONFIG_SYS_RCAR_I2C0_SPEED 400000 63*4882a593Smuzhiyun #define CONFIG_SYS_RCAR_I2C1_SPEED 400000 64*4882a593Smuzhiyun #define CONFIG_SYS_RCAR_I2C2_SPEED 400000 65*4882a593Smuzhiyun #define CONFIG_SYS_RCAR_I2C3_SPEED 400000 66*4882a593Smuzhiyun #define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* Board Clock */ 71*4882a593Smuzhiyun #define RMOBILE_XTAL_CLK 20000000u 72*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK 73*4882a593Smuzhiyun #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ 74*4882a593Smuzhiyun #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) 75*4882a593Smuzhiyun #define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2) 76*4882a593Smuzhiyun #define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15) 77*4882a593Smuzhiyun #define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define CONFIG_SYS_TMU_CLK_DIV 4 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* USB */ 82*4882a593Smuzhiyun #define CONFIG_USB_EHCI_RMOBILE 83*4882a593Smuzhiyun #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* Module stop status bits */ 86*4882a593Smuzhiyun /* INTC-RT */ 87*4882a593Smuzhiyun #define CONFIG_SMSTP0_ENA 0x00400000 88*4882a593Smuzhiyun /* MSIF, SCIFA0 */ 89*4882a593Smuzhiyun #define CONFIG_SMSTP2_ENA 0x00002010 90*4882a593Smuzhiyun /* INTC-SYS, IRQC */ 91*4882a593Smuzhiyun #define CONFIG_SMSTP4_ENA 0x00000180 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* SDHI */ 94*4882a593Smuzhiyun #define CONFIG_SH_SDHI_FREQ 97500000 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #endif /* __STOUT_H */ 97